24-12-2012, 04:44 PM
ACCNT: A Metallic-CNT-Tolerant Design Methodology for Carbon Nanotube VLSI: Analyses and Design Guidelines
[attachment=45155]
Abstract
We present analyses for ACCNT (pronounced as
“accent”), which is a solution to the metallic-nanotube problem
that does not require any metallic-nanotube removal of any
kind. ACCNT uses asymmetrically correlated carbon nanotubes
to achieve metallic-nanotube tolerance, delivering high ON–OFF
ratios while preserving current drive. We analyze the ACCNT
methodology in terms of its tradeoffs and explore optimizations
that may serve as future design guidelines. We also investigate
circuit-level considerations and the impact of density variation on
the ACCNT design.We find that ACCNT can improve the yield of
a one-million transistor chip from 0% (conventional CNT design)
up to 99% at a cost of 3.3× area overhead if the fraction of
semiconducting CNTs is improved to 99.9%.
INTRODUCTION
CARBON nanotube field-effect transistor (CNFET) technology
has received much attention in the past few years
as a candidate for future integrated circuits [1]. To realize the
potential of CNFETs, robust and scalable CNFET technologies
must be developed. While recent research has advanced CNFET
technology past many important milestones, one milestone has
yet to be achieved, i.e., a robust and VLSI-compatible solution
to the presence of metallic carbon nanotubes (CNTs).
CNTs can be either semiconducting or metallic; semiconducting
CNTs are useful as a field-effect transistor (FET)
channel material, whereas metallic CNTs in the channel cause
shorts between the source and the drain. In typical experiments,
semiconducting percentages of approximately only 50%–75%
(25%–50% metallic CNTs) can be inferred [2], [3]. Thus,
metallic CNTs pose a big problem.
OPTIMAL SOLUTIONS AND DESIGN FLOW
In this section, we investigate ACCNT optimality. Since the
optimization problem is very much dependent on the specific
scenario, we omit lengthy discussions of every possibility;
rather, we present the following optimization analyses and
formulate a few design guidelines based on these analyses.
This then serves as a general analytical framework for deriving
solutions to other specific scenarios.
Constraints for Optimal Designs
To establish design guidelines, we begin by analyzing constraints
and bounds for Pareto optimality. Specifically, in the
following, we will analyze several scenarios to derive a few
necessary conditions for a Pareto-optimal ACCNT CNFET design.
By understanding these conditions, we are able to present
methods for improving a design to be Pareto optimal, if given a
suboptimal design that does not meet these conditions.
First, we will show that designs with a large NCNT (above a
certain cutoff) are not Pareto optimal, and there exists a design
with a smaller NCNT that has a better (higher) POverallSemi
while still having the same Idrive and area. Thus, this new
design is better (a Pareto improvement in the context of strong
Pareto optimality) and consequently preferable over the original
design.
Design Flow for a Pareto-Optimal ACCNT CNFET
Following from the preceding analyses on constraints, we
can now begin to formulate the design flow. Note that the
preceding analyses have yet to consider the discrete/quantized
nature of the design variables, i.e., nrows, mcols, and NCNT
must be integers greater than or equal to one. One approach
would be to first find a continuous-domain solution (without
limiting the design variables to integers) and then round the
solution to the nearest discrete-domain solution (where each
design variable is an integer) for implementation. However,
since POverallSemi, Idrive, and the area are very sensitive to
changes in nrows, mcols, and NCNT, rounding a continuousdomain
Pareto-optimal solution to the nearest discrete-domain
solution often does not result in the discrete-domain Paretooptimal
solution. Consequently, a reasonable strategy for finding
the set of Pareto-optimal solutions is to enumerate a set of
possible solutions and evaluate them to find the best ones.
Noise Margin Violations
In the previous sections, the probability of metallic-CNT
tolerance (POverallSemi, which is defined as the probability that
the ACCNT CNFET has a high ON–OFF ratio) was used as a
figure of merit. This metric is useful in situations where strict
high ON–OFF ratios are required at the device level. However,
on the circuit level, correct logic functionality is often the primary
concern. Even if, occasionally, a few comprising devices
have slightly lower-than-desired ON–OFF ratios, as long as
the overall circuit performs correctly, then that is acceptable.
Thus, on the circuit level, perhaps a more relevant metric is
the probability that the noise margin requirements are met, as
opposed to the probability that every transistor in the circuit
has a high ON–OFF ratio1. For ease of plotting and without
loss of generality, we look at the opposite metric, which is the
probability of noise margin violation (PNMV).
CONCLUSION
We have presented several analyses in this work for ACCNT,
which is a metallic-CNT-tolerant design solution using asymmetrically
correlated CNTs. We have also presented the analytical
framework and illustrated its use using specific scenarios
with specific parameter values. However, an infinite number of
scenarios exist and are complicated by the numerous ways to
factor in nonidealities. We have hereby concluded this work on
ACCNT analyses and noted that, while we have not explored
every possible scenario, various other scenarios can be analyzed
using the analytical framework and design flow presented
herein.
In addition to shedding light on ACCNT, the analyses herein
have also highlighted another very important conclusion: the
quality of current CNT materials is insufficient for CNT digital
logic circuits (even with solutions such as ACCNT, the area
cost may be too large for the current psemi). We must improve
the CNT material and/or employ a hybrid solution, which combines
ACCNT with other material-improving processes (e.g.,
selective etching [15], sorting [16], [17], or electrical breakdown
[21]–[23]). Once the semiconducting-CNT percentage is
improved to 99.9%, ACCNT offers a solution to significantly
reduce the “metallic-CNT-induced yield loss” and the PNMV,
which otherwise would cause conventionally designed circuits
to completely fail. Furthermore, the ACCNT area costs can
significantly be reduced by optimizing the ACCNT design—we
find that ACCNT can improve the chip yield of a one-million
transistor chip from 0% (that using a conventional design) to
99% with an area overhead of about 3.3×.
[attachment=45155]
Abstract
We present analyses for ACCNT (pronounced as
“accent”), which is a solution to the metallic-nanotube problem
that does not require any metallic-nanotube removal of any
kind. ACCNT uses asymmetrically correlated carbon nanotubes
to achieve metallic-nanotube tolerance, delivering high ON–OFF
ratios while preserving current drive. We analyze the ACCNT
methodology in terms of its tradeoffs and explore optimizations
that may serve as future design guidelines. We also investigate
circuit-level considerations and the impact of density variation on
the ACCNT design.We find that ACCNT can improve the yield of
a one-million transistor chip from 0% (conventional CNT design)
up to 99% at a cost of 3.3× area overhead if the fraction of
semiconducting CNTs is improved to 99.9%.
INTRODUCTION
CARBON nanotube field-effect transistor (CNFET) technology
has received much attention in the past few years
as a candidate for future integrated circuits [1]. To realize the
potential of CNFETs, robust and scalable CNFET technologies
must be developed. While recent research has advanced CNFET
technology past many important milestones, one milestone has
yet to be achieved, i.e., a robust and VLSI-compatible solution
to the presence of metallic carbon nanotubes (CNTs).
CNTs can be either semiconducting or metallic; semiconducting
CNTs are useful as a field-effect transistor (FET)
channel material, whereas metallic CNTs in the channel cause
shorts between the source and the drain. In typical experiments,
semiconducting percentages of approximately only 50%–75%
(25%–50% metallic CNTs) can be inferred [2], [3]. Thus,
metallic CNTs pose a big problem.
OPTIMAL SOLUTIONS AND DESIGN FLOW
In this section, we investigate ACCNT optimality. Since the
optimization problem is very much dependent on the specific
scenario, we omit lengthy discussions of every possibility;
rather, we present the following optimization analyses and
formulate a few design guidelines based on these analyses.
This then serves as a general analytical framework for deriving
solutions to other specific scenarios.
Constraints for Optimal Designs
To establish design guidelines, we begin by analyzing constraints
and bounds for Pareto optimality. Specifically, in the
following, we will analyze several scenarios to derive a few
necessary conditions for a Pareto-optimal ACCNT CNFET design.
By understanding these conditions, we are able to present
methods for improving a design to be Pareto optimal, if given a
suboptimal design that does not meet these conditions.
First, we will show that designs with a large NCNT (above a
certain cutoff) are not Pareto optimal, and there exists a design
with a smaller NCNT that has a better (higher) POverallSemi
while still having the same Idrive and area. Thus, this new
design is better (a Pareto improvement in the context of strong
Pareto optimality) and consequently preferable over the original
design.
Design Flow for a Pareto-Optimal ACCNT CNFET
Following from the preceding analyses on constraints, we
can now begin to formulate the design flow. Note that the
preceding analyses have yet to consider the discrete/quantized
nature of the design variables, i.e., nrows, mcols, and NCNT
must be integers greater than or equal to one. One approach
would be to first find a continuous-domain solution (without
limiting the design variables to integers) and then round the
solution to the nearest discrete-domain solution (where each
design variable is an integer) for implementation. However,
since POverallSemi, Idrive, and the area are very sensitive to
changes in nrows, mcols, and NCNT, rounding a continuousdomain
Pareto-optimal solution to the nearest discrete-domain
solution often does not result in the discrete-domain Paretooptimal
solution. Consequently, a reasonable strategy for finding
the set of Pareto-optimal solutions is to enumerate a set of
possible solutions and evaluate them to find the best ones.
Noise Margin Violations
In the previous sections, the probability of metallic-CNT
tolerance (POverallSemi, which is defined as the probability that
the ACCNT CNFET has a high ON–OFF ratio) was used as a
figure of merit. This metric is useful in situations where strict
high ON–OFF ratios are required at the device level. However,
on the circuit level, correct logic functionality is often the primary
concern. Even if, occasionally, a few comprising devices
have slightly lower-than-desired ON–OFF ratios, as long as
the overall circuit performs correctly, then that is acceptable.
Thus, on the circuit level, perhaps a more relevant metric is
the probability that the noise margin requirements are met, as
opposed to the probability that every transistor in the circuit
has a high ON–OFF ratio1. For ease of plotting and without
loss of generality, we look at the opposite metric, which is the
probability of noise margin violation (PNMV).
CONCLUSION
We have presented several analyses in this work for ACCNT,
which is a metallic-CNT-tolerant design solution using asymmetrically
correlated CNTs. We have also presented the analytical
framework and illustrated its use using specific scenarios
with specific parameter values. However, an infinite number of
scenarios exist and are complicated by the numerous ways to
factor in nonidealities. We have hereby concluded this work on
ACCNT analyses and noted that, while we have not explored
every possible scenario, various other scenarios can be analyzed
using the analytical framework and design flow presented
herein.
In addition to shedding light on ACCNT, the analyses herein
have also highlighted another very important conclusion: the
quality of current CNT materials is insufficient for CNT digital
logic circuits (even with solutions such as ACCNT, the area
cost may be too large for the current psemi). We must improve
the CNT material and/or employ a hybrid solution, which combines
ACCNT with other material-improving processes (e.g.,
selective etching [15], sorting [16], [17], or electrical breakdown
[21]–[23]). Once the semiconducting-CNT percentage is
improved to 99.9%, ACCNT offers a solution to significantly
reduce the “metallic-CNT-induced yield loss” and the PNMV,
which otherwise would cause conventionally designed circuits
to completely fail. Furthermore, the ACCNT area costs can
significantly be reduced by optimizing the ACCNT design—we
find that ACCNT can improve the chip yield of a one-million
transistor chip from 0% (that using a conventional design) to
99% with an area overhead of about 3.3×.