29-12-2012, 02:50 PM
INTEL 8251
[attachment=45790]
ABSTRACT
The INTEL 8251, USART (universal synchronous asynchronous receiver and transmitter) module provides asynchronous serial communication with external devices such as modems and other computers. The INTEL 8251 can be used to control the process of breaking parallel data from the PC down into serial data that can be transmitted and vice versa for receiving data. The INTEL 8251 allows the devices to communicate without the need to be synchronized.
A parallel link transmits several streams of data 8 (perhaps representing particular bits of a stream of bytes) along multiple channels (wires printed circuit tracks, optical fibers, etc.); a serial link transmits a single stream of data in telecommunications and computer. Science, serial communications is the process sending data one bit at one time sequentially, over a communications channel computer bus.
This is in contrast to parallel communications, where all the bits of each symbol are sent together. Serial communications is used for all long –haul communications and most computer networks. Where the cost of cable an synchronization difficulties make parallel communications impractical.
GENERAL DESCRIPTION
The INTEL 8251 is a usart (universal synchronous asynchronous receiver transmitter) for serial data communication.
As a peripheral device of a micro computer system the MSM 82 C51A-2 receives parallel data from the CPU & transmits serial data after conversion. This device also receives serial data from the outside & transmit parallel data the CPU after conversion.
FEATURES
wide power supply voltage range from 3v-6v
wide temperature range from -400C to 850C
synchronous communication up to 64 Kbaud
asynchronous communication up to 38.4 Kbaud
transmitting/receiving operations under double buffered configuration.
error detection (parity, over run, framing )
PIN DESCRIPTION
D 0 to D 7 (l/O terminal)
This is bidirectional data bus which receive control words and transmits data from the CPU and sends status words and received data to CPU.
RESET (Input terminal)
A "High" on this input forces the 8251 into "reset status." The device waits for the writing of "mode instruction." The min. reset width is six clock inputs during the operating status of CLK.
CLK (Input terminal)
CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC. However, the frequency of CLK must be greater than 30 times the RXC and TXC at Synchronous mode and Asynchronous "x1" mode, and must be greater than 5 times at Asynchronous "x16" and "x64" mode.
WR (Input terminal)
This is the "active low" input terminal which receives a signal for writing transmit data and control words from the CPU into the 8251.
RD (Input terminal)
This is the "active low" input terminal which receives a signal for reading receive data and status words from the 8251.
C/D (Input terminal)
This is an input terminal which receives a signal for selecting data or command words and status words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high, command word or status word will be accessed.
CS (Input terminal)
This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses. Note: The device won’t be in "standby status"; only setting CS = High.
[attachment=45790]
ABSTRACT
The INTEL 8251, USART (universal synchronous asynchronous receiver and transmitter) module provides asynchronous serial communication with external devices such as modems and other computers. The INTEL 8251 can be used to control the process of breaking parallel data from the PC down into serial data that can be transmitted and vice versa for receiving data. The INTEL 8251 allows the devices to communicate without the need to be synchronized.
A parallel link transmits several streams of data 8 (perhaps representing particular bits of a stream of bytes) along multiple channels (wires printed circuit tracks, optical fibers, etc.); a serial link transmits a single stream of data in telecommunications and computer. Science, serial communications is the process sending data one bit at one time sequentially, over a communications channel computer bus.
This is in contrast to parallel communications, where all the bits of each symbol are sent together. Serial communications is used for all long –haul communications and most computer networks. Where the cost of cable an synchronization difficulties make parallel communications impractical.
GENERAL DESCRIPTION
The INTEL 8251 is a usart (universal synchronous asynchronous receiver transmitter) for serial data communication.
As a peripheral device of a micro computer system the MSM 82 C51A-2 receives parallel data from the CPU & transmits serial data after conversion. This device also receives serial data from the outside & transmit parallel data the CPU after conversion.
FEATURES
wide power supply voltage range from 3v-6v
wide temperature range from -400C to 850C
synchronous communication up to 64 Kbaud
asynchronous communication up to 38.4 Kbaud
transmitting/receiving operations under double buffered configuration.
error detection (parity, over run, framing )
PIN DESCRIPTION
D 0 to D 7 (l/O terminal)
This is bidirectional data bus which receive control words and transmits data from the CPU and sends status words and received data to CPU.
RESET (Input terminal)
A "High" on this input forces the 8251 into "reset status." The device waits for the writing of "mode instruction." The min. reset width is six clock inputs during the operating status of CLK.
CLK (Input terminal)
CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC. However, the frequency of CLK must be greater than 30 times the RXC and TXC at Synchronous mode and Asynchronous "x1" mode, and must be greater than 5 times at Asynchronous "x16" and "x64" mode.
WR (Input terminal)
This is the "active low" input terminal which receives a signal for writing transmit data and control words from the CPU into the 8251.
RD (Input terminal)
This is the "active low" input terminal which receives a signal for reading receive data and status words from the 8251.
C/D (Input terminal)
This is an input terminal which receives a signal for selecting data or command words and status words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high, command word or status word will be accessed.
CS (Input terminal)
This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses. Note: The device won’t be in "standby status"; only setting CS = High.