29-12-2012, 06:44 PM
Design of High Speed 32 Bit Truncation-Error-
Tolerant Adder
[attachment=45884]
INTRODUCTION
In conventional digital VLSI design, one
usually assumes that a usable circuit/system should
always provide definite and accurate results. But in
fact, such perfect operations are seldom needed in our
non digital worldly experiences. The world accepts
“analog computation,” which generates “good
enough” results rather than totally accurate results
[1]. The data processed by many digital systems may
already contain errors. In many applications, such as
a communication system, the analog signal coming
from the outside world must first be sampled before
being converted to digital data. The digital data are
then processed and transmitted in a noisy channel
before converting back to an analog signal.
During this process, errors may occur
anywhere. Furthermore, due to the advances in
transistor size scaling, factors such as noise and
process variations which are previously insignificant
are becoming important in today’s digital IC design
[2]. Based on the characteristic of digital VLSI
design, some novel concepts and design techniques
have been proposed.
This is to preserve its correctness since the
higher order bits play a more important role than the
lower order bits. The lower order bits of input
operands (inaccurate part) are added using error
tolerant addition mechanism. No carry signal will be
generated or taken in at any bit position to eliminate
the carry propagation path. To minimize the overall
error due to the elimination of the carry chain, a
special strategy is adapted (Zhu et al., 2010), and can
be described as follows:
Check every bit position from left to right
(MSB - LSB) starting from right of
demarcation line;
If both input bits are “0” or different, normal
one-bit addition is performed and the
operation proceeds to next bit position;
The checking process is stopped when both
input bits are encountered as high i.e., 1, and
from this bit onwards, all sum bits to the
right (LSB) are set to “1.”
DESIGN OF A 32-BIT ERROR-TOLERANT ADDER
The first step of designing a proposed ETA
is to divide the adder into two parts in a specific
manner. The dividing strategy is based on a guessand-
verify stratagem, depending on the requirements,
such as accuracy, speed, and power.
With this partition method defined, we then
check whether the accuracy performance of the adder
meets the requirements preset by designer/ customer.
This can be checked very quickly via some software
programs. For example, for a specific application, we
require the minimum acceptable accuracy to be 95%
and the acceptance probability to be 98%. The
proposed partition method must therefore have at
least 98% of all possible inputs reaching an accuracy
of better than 95%. If this requirement is not met,
then one bit should be shifted from the inaccurate
part to the accurate part and have the checking
process repeated. Also, due to the simplified circuit
structure and the elimination of switching activities in
the inaccurate part, putting more bits in this part
yields more power saving. Having considered the
above, we divided the 32-bit adder by putting 12 bits
in the accurate part and 20 bits in the inaccurate part.
RESULTS
The proposed 32 bit ET Adder is designed in
XILINX 9.2 using VERILOG HDL code and
simulated using Modelsim 6.5e To evaluate the
efficiency of the proposed architecture
Tolerant Adder
[attachment=45884]
INTRODUCTION
In conventional digital VLSI design, one
usually assumes that a usable circuit/system should
always provide definite and accurate results. But in
fact, such perfect operations are seldom needed in our
non digital worldly experiences. The world accepts
“analog computation,” which generates “good
enough” results rather than totally accurate results
[1]. The data processed by many digital systems may
already contain errors. In many applications, such as
a communication system, the analog signal coming
from the outside world must first be sampled before
being converted to digital data. The digital data are
then processed and transmitted in a noisy channel
before converting back to an analog signal.
During this process, errors may occur
anywhere. Furthermore, due to the advances in
transistor size scaling, factors such as noise and
process variations which are previously insignificant
are becoming important in today’s digital IC design
[2]. Based on the characteristic of digital VLSI
design, some novel concepts and design techniques
have been proposed.
This is to preserve its correctness since the
higher order bits play a more important role than the
lower order bits. The lower order bits of input
operands (inaccurate part) are added using error
tolerant addition mechanism. No carry signal will be
generated or taken in at any bit position to eliminate
the carry propagation path. To minimize the overall
error due to the elimination of the carry chain, a
special strategy is adapted (Zhu et al., 2010), and can
be described as follows:
Check every bit position from left to right
(MSB - LSB) starting from right of
demarcation line;
If both input bits are “0” or different, normal
one-bit addition is performed and the
operation proceeds to next bit position;
The checking process is stopped when both
input bits are encountered as high i.e., 1, and
from this bit onwards, all sum bits to the
right (LSB) are set to “1.”
DESIGN OF A 32-BIT ERROR-TOLERANT ADDER
The first step of designing a proposed ETA
is to divide the adder into two parts in a specific
manner. The dividing strategy is based on a guessand-
verify stratagem, depending on the requirements,
such as accuracy, speed, and power.
With this partition method defined, we then
check whether the accuracy performance of the adder
meets the requirements preset by designer/ customer.
This can be checked very quickly via some software
programs. For example, for a specific application, we
require the minimum acceptable accuracy to be 95%
and the acceptance probability to be 98%. The
proposed partition method must therefore have at
least 98% of all possible inputs reaching an accuracy
of better than 95%. If this requirement is not met,
then one bit should be shifted from the inaccurate
part to the accurate part and have the checking
process repeated. Also, due to the simplified circuit
structure and the elimination of switching activities in
the inaccurate part, putting more bits in this part
yields more power saving. Having considered the
above, we divided the 32-bit adder by putting 12 bits
in the accurate part and 20 bits in the inaccurate part.
RESULTS
The proposed 32 bit ET Adder is designed in
XILINX 9.2 using VERILOG HDL code and
simulated using Modelsim 6.5e To evaluate the
efficiency of the proposed architecture