01-01-2013, 02:33 PM
BIOMETRIC VOTING MACHINE
INTRODUCTION:
The objective of voting is to allow voters to exercise their right to express their choices regarding specific issues, pieces of legislation, citizen initiatives, constitutional amendments, recalls and/or to choose their government and political representatives. Technology is being used more and more as a tool to assist voters to cast their votes. To allow the exercise of this right, almost all voting systems around the world include the following steps:
voter identification and authentication
voting and recording of votes cast
vote counting
publication of election results
Voter identification is required during two phases of the electoral process: first for voter registration in order to establish the right to vote and afterwards, at voting time, to allow a citizen to exercise their right to vote by verifying if the person satisfies all the requirements needed to vote (authentication).
Ancient archeological artifacts and historical items have been discovered to still retain a large number of fingerprints on them. Since this was a discovered significant stride in fingerprinting and identification have been made. In 1788 a detailed description of anatomical formations of fingerprints was made. Then in1823 fingerprints began to be classified into nine categories, (Handbook) and by the 19th century Sir Francis Galton had developed analytical methods for fingerprint matching. As the criminal justice system evolved, there arose the need for criminals to be uniquely identified by some physically identifiable trait. Richard Edward Henry of Scotland Yard began using fingerprinting in 1901 and its success eventually lead to its increased use in the law enforcement field
The field of biometrics was formed and has since expanded on to many types of physical identification. Still, the human fingerprint remains a very common identifier and the biometric method of choice among law enforcement. These concepts of human identification have lead to the development of fingerprint scanners that serve to quickly identify individuals and assign access privileges. The basic point of these devices is also to examine the fingerprint data of an individual and compare it to a database of other fingerprints.
HARDWARE DESCRIPTION:
Biometric Voting Machine hardware mainly contains a microcontroller, finger print module, eeprom, lcd display, PC interface, power supply, key pad. Each of the components are described below.
MICROCONTROLLER- AT89C52:
The 8952 microcontroller is upgraded version of 8051 family of microcontrollers. The 8051 microcontroller was introduced by Intel Corporation in the year 1981. It is an 8-bit microcontroller with Harvard Architecture manufactured by advanced CMOS processes. It has 128 bytes of on chip RAM, 4k bytes of on chip ROM, two 16-bit timers/counters, four 8-bit ports of which one is a serial port, etc. There are 6 interrupt sources also.
Since this is an 8-bit micro controller, the CPU can work on only 8 bits of data at a time. Data larger than 8 bits has to be broken down to 8 bit pieces. Though it has an addressing capability of 64 Kbytes, only 4k bytes have been provided on chip.
8051 is available in different memory types, such as UV-EPROM, FLASH, and NV-RAM. The UV-EPROM version of 8051 is the 8751. This chip has only 4K bytes of on chip UV-EPROM. To use this chip for development requires access to a PROM burner, as well as a UV-EPROM eraser to erase all the contents of UV-EPROM inside the 8751 chip before you can program it again. It takes about 20 minutes to erase the 8751 before it can be programmed again. This led to introduce FLASH and NV-RAM versions of 8051.
Another popular version of 8051 is DS5000 chip from Dallas Semiconductor. The on chip ROM is in the form of NV-RAM. The read/write capability of NV-RAM allows the program to be loaded into the on chip ROM while in the system. This can be done via a serial port of a PC. Another advantage of NV-RAM is the ability to change the ROM contents one byte at a time. The entire ROM must be erased before programmed again in the case of UV-EPROM and flash memory.
89C52 Oscillator and Clock
The heart of 89C51 is the circuitry that generates the clock pulses by which all internal operations are synchronized. Pins XTAL1 and XTAL2 are provided for connecting a resonant network to form an oscillator. The crystal frequency is the basic internal clock frequency of the micro controller.
Program Counter and Data Pointer
The 89C52 contains two 16 bit registers, the program counter and the data counter. Each is used to hold the address of byte in memory. Program instruction byte is fetched from location in memory that is addressed by the PC. The PC is automatically incremented after every instruction bytes fetched and may also be altered by certain instructions.
The DPTR register is made up of two 8-bit registers named DPH and DPL, which are used to furnish memory addresses for internal and external code access and external access. The DPTR is under the control of program instructions.
A & B CPU registers:
The A and B register holds results of many operations, particularly math and logical operations. The A register is also used for all data transfers between the 89C51 and any external memory.
Flags & Program Status Word:
Flags are 1 bit registers provided to store the result of certain program instructions. The flags are groups inside the program status word and the power control (PCON) registers. The 89C52 have four math flags that respond automatically to the result of math operation and three general-purpose user flags that can be set to 1 or cleared to 0 by the programmer as desired. The math flag include carry ©, Auxiliary Carry (AC), Overflow (OV) and Parity (P). User flags are named F0, GF0 and GF1; they are general purpose flags hat may be used by the programmer to record some event in the program.
The program status word contains the math flag, user program flag F0, and the register select bits identify which of the four general purpose register banks is currently in use by the program.
Internal Memory:
The 89C52 have internal RAM for program code bytes and for variable data that can be altered as the program runs. Additional memory can be added externally using suitable circuits. Unlike micro-controller with a Von Neumann architecture, which can use a single memory address for either program code or data, but not for both, the 89C52 have Harvard architecture, which uses the same address, in different memories, for code and data. Internal security accesses the correct memory based on the nature of operation in progress.
Internal RAM:
It had 128 internal RAM, which is organized, into distinct areas. 32 bytes from address 00H to 1FH that make up thirty two working registers organized as four bands of eight registers each. A bit addressable area of sixteen bytes occupies ram byte addresses 20H to 2FH. A general purpose RAM area above the bit area from 30H to 7FH addressable as bytes.
Stack and Stack Pointer:
The stack refers to an area of internal ram that is used in conjunction with certain op codes to store and retrieve data quickly. The eight-bit stack pointer register is used to hold an internal ram address called the top of the stack. The address held in the SP register is the location in the internal ram where the last byte of data was stored by a stack operation.
When data is to be placed on the stack the SP increments before storing data on the stack up grows, as data is stored. As data is retrieved from the stack, the byte is read from the stack, and then the SP decrements to point to the next available byte of stored data. The SP is set to 07H when the 89C52 is reset and can be changed to any internal ram addressed by the programmer.
Counters and Timers:
Many microcontroller applications require the counting of external events such as frequency of pulse train, or the generation of precise internal time delays between computer actions. Three sixteen bit counters named T0,T1and T2 are provided for general use of the programmer. Each counter may be programmed to count internal clock pulses acting as a timer or program to count external pulses as a counter.
The counters are divided into eight bit registers called the timer low (TL0, TL1) and high (TH0, TH1) bytes. All counter actions is controlled by bit status in the timer mode control registers TMOD, the timer/counter control register TCON, and certain program instructions.
TMOD is dedicated entirely to the timer and can be considered to be two duplicate 4 bit registers, each of which controls the action of one of the timer. TCON has the control bits and flags for the timer in the upper nibble, control bits and flags for external interrupts in the lower nibble.
Timer Counter Interrupts:
The timers have been included on the chip to relieve the processor of timing and counting chores. When the program wished to count a certain number of internal pulses or external events, a number is placed in one of the counters. The number represents the maximum count less the decide count, plus 1.The counter increments from the initial number to the maximum and then roles over to 0 on the final pulse and also set a timer flag. The flag condition may be tested by an instruction to tell the program that the count has been accomplished, or the flag may be used to interrupt the program.
Interrupts:
Interrupts are hardware signals that force a program to call a subroutine. Interrupts take up the processor time only when the action by the program is needed. Interrupts are often the only way in which real time programming can be done successfully.
Interrupts may be generated by internal chip operation or by external sources. Any interrupt can cause the microcontroller to perform a hardware call to an interrupt handling subroutine that is located at a pre determined absolute address in the program memory. Five interrupts are provided in the 8051. Three of these are generated automatically by interrupt (R1 or T1). Two interrupts are triggered by external signals provided by circuitry that is connected to pins INT0 and INT1.
All interrupts are under the control of the program. The programmer is able to alter the control bits in the Interrupt Enable register (IE), the Interrupt Priority register (IP) and the Timer Control register (TCON). The program can block all or any of the combinations of the interrupt from acting on the program by suitable setting or clearing of these registers. After the interrupts has been handled by the interrupt subroutine, which is placed by the programmer in the interrupt location in the program memory, the interrupt program must resume operation at the instruction where the interrupt take place. Program resumption is done by storing the interrupted PC address on the stack in ram before changing the PC to the interrupt address in ROM. The PC address will be stored from the stack after an RETI instruction is executed at the end of the interrupt subroutine.
INTRODUCTION:
The objective of voting is to allow voters to exercise their right to express their choices regarding specific issues, pieces of legislation, citizen initiatives, constitutional amendments, recalls and/or to choose their government and political representatives. Technology is being used more and more as a tool to assist voters to cast their votes. To allow the exercise of this right, almost all voting systems around the world include the following steps:
voter identification and authentication
voting and recording of votes cast
vote counting
publication of election results
Voter identification is required during two phases of the electoral process: first for voter registration in order to establish the right to vote and afterwards, at voting time, to allow a citizen to exercise their right to vote by verifying if the person satisfies all the requirements needed to vote (authentication).
Ancient archeological artifacts and historical items have been discovered to still retain a large number of fingerprints on them. Since this was a discovered significant stride in fingerprinting and identification have been made. In 1788 a detailed description of anatomical formations of fingerprints was made. Then in1823 fingerprints began to be classified into nine categories, (Handbook) and by the 19th century Sir Francis Galton had developed analytical methods for fingerprint matching. As the criminal justice system evolved, there arose the need for criminals to be uniquely identified by some physically identifiable trait. Richard Edward Henry of Scotland Yard began using fingerprinting in 1901 and its success eventually lead to its increased use in the law enforcement field
The field of biometrics was formed and has since expanded on to many types of physical identification. Still, the human fingerprint remains a very common identifier and the biometric method of choice among law enforcement. These concepts of human identification have lead to the development of fingerprint scanners that serve to quickly identify individuals and assign access privileges. The basic point of these devices is also to examine the fingerprint data of an individual and compare it to a database of other fingerprints.
HARDWARE DESCRIPTION:
Biometric Voting Machine hardware mainly contains a microcontroller, finger print module, eeprom, lcd display, PC interface, power supply, key pad. Each of the components are described below.
MICROCONTROLLER- AT89C52:
The 8952 microcontroller is upgraded version of 8051 family of microcontrollers. The 8051 microcontroller was introduced by Intel Corporation in the year 1981. It is an 8-bit microcontroller with Harvard Architecture manufactured by advanced CMOS processes. It has 128 bytes of on chip RAM, 4k bytes of on chip ROM, two 16-bit timers/counters, four 8-bit ports of which one is a serial port, etc. There are 6 interrupt sources also.
Since this is an 8-bit micro controller, the CPU can work on only 8 bits of data at a time. Data larger than 8 bits has to be broken down to 8 bit pieces. Though it has an addressing capability of 64 Kbytes, only 4k bytes have been provided on chip.
8051 is available in different memory types, such as UV-EPROM, FLASH, and NV-RAM. The UV-EPROM version of 8051 is the 8751. This chip has only 4K bytes of on chip UV-EPROM. To use this chip for development requires access to a PROM burner, as well as a UV-EPROM eraser to erase all the contents of UV-EPROM inside the 8751 chip before you can program it again. It takes about 20 minutes to erase the 8751 before it can be programmed again. This led to introduce FLASH and NV-RAM versions of 8051.
Another popular version of 8051 is DS5000 chip from Dallas Semiconductor. The on chip ROM is in the form of NV-RAM. The read/write capability of NV-RAM allows the program to be loaded into the on chip ROM while in the system. This can be done via a serial port of a PC. Another advantage of NV-RAM is the ability to change the ROM contents one byte at a time. The entire ROM must be erased before programmed again in the case of UV-EPROM and flash memory.
89C52 Oscillator and Clock
The heart of 89C51 is the circuitry that generates the clock pulses by which all internal operations are synchronized. Pins XTAL1 and XTAL2 are provided for connecting a resonant network to form an oscillator. The crystal frequency is the basic internal clock frequency of the micro controller.
Program Counter and Data Pointer
The 89C52 contains two 16 bit registers, the program counter and the data counter. Each is used to hold the address of byte in memory. Program instruction byte is fetched from location in memory that is addressed by the PC. The PC is automatically incremented after every instruction bytes fetched and may also be altered by certain instructions.
The DPTR register is made up of two 8-bit registers named DPH and DPL, which are used to furnish memory addresses for internal and external code access and external access. The DPTR is under the control of program instructions.
A & B CPU registers:
The A and B register holds results of many operations, particularly math and logical operations. The A register is also used for all data transfers between the 89C51 and any external memory.
Flags & Program Status Word:
Flags are 1 bit registers provided to store the result of certain program instructions. The flags are groups inside the program status word and the power control (PCON) registers. The 89C52 have four math flags that respond automatically to the result of math operation and three general-purpose user flags that can be set to 1 or cleared to 0 by the programmer as desired. The math flag include carry ©, Auxiliary Carry (AC), Overflow (OV) and Parity (P). User flags are named F0, GF0 and GF1; they are general purpose flags hat may be used by the programmer to record some event in the program.
The program status word contains the math flag, user program flag F0, and the register select bits identify which of the four general purpose register banks is currently in use by the program.
Internal Memory:
The 89C52 have internal RAM for program code bytes and for variable data that can be altered as the program runs. Additional memory can be added externally using suitable circuits. Unlike micro-controller with a Von Neumann architecture, which can use a single memory address for either program code or data, but not for both, the 89C52 have Harvard architecture, which uses the same address, in different memories, for code and data. Internal security accesses the correct memory based on the nature of operation in progress.
Internal RAM:
It had 128 internal RAM, which is organized, into distinct areas. 32 bytes from address 00H to 1FH that make up thirty two working registers organized as four bands of eight registers each. A bit addressable area of sixteen bytes occupies ram byte addresses 20H to 2FH. A general purpose RAM area above the bit area from 30H to 7FH addressable as bytes.
Stack and Stack Pointer:
The stack refers to an area of internal ram that is used in conjunction with certain op codes to store and retrieve data quickly. The eight-bit stack pointer register is used to hold an internal ram address called the top of the stack. The address held in the SP register is the location in the internal ram where the last byte of data was stored by a stack operation.
When data is to be placed on the stack the SP increments before storing data on the stack up grows, as data is stored. As data is retrieved from the stack, the byte is read from the stack, and then the SP decrements to point to the next available byte of stored data. The SP is set to 07H when the 89C52 is reset and can be changed to any internal ram addressed by the programmer.
Counters and Timers:
Many microcontroller applications require the counting of external events such as frequency of pulse train, or the generation of precise internal time delays between computer actions. Three sixteen bit counters named T0,T1and T2 are provided for general use of the programmer. Each counter may be programmed to count internal clock pulses acting as a timer or program to count external pulses as a counter.
The counters are divided into eight bit registers called the timer low (TL0, TL1) and high (TH0, TH1) bytes. All counter actions is controlled by bit status in the timer mode control registers TMOD, the timer/counter control register TCON, and certain program instructions.
TMOD is dedicated entirely to the timer and can be considered to be two duplicate 4 bit registers, each of which controls the action of one of the timer. TCON has the control bits and flags for the timer in the upper nibble, control bits and flags for external interrupts in the lower nibble.
Timer Counter Interrupts:
The timers have been included on the chip to relieve the processor of timing and counting chores. When the program wished to count a certain number of internal pulses or external events, a number is placed in one of the counters. The number represents the maximum count less the decide count, plus 1.The counter increments from the initial number to the maximum and then roles over to 0 on the final pulse and also set a timer flag. The flag condition may be tested by an instruction to tell the program that the count has been accomplished, or the flag may be used to interrupt the program.
Interrupts:
Interrupts are hardware signals that force a program to call a subroutine. Interrupts take up the processor time only when the action by the program is needed. Interrupts are often the only way in which real time programming can be done successfully.
Interrupts may be generated by internal chip operation or by external sources. Any interrupt can cause the microcontroller to perform a hardware call to an interrupt handling subroutine that is located at a pre determined absolute address in the program memory. Five interrupts are provided in the 8051. Three of these are generated automatically by interrupt (R1 or T1). Two interrupts are triggered by external signals provided by circuitry that is connected to pins INT0 and INT1.
All interrupts are under the control of the program. The programmer is able to alter the control bits in the Interrupt Enable register (IE), the Interrupt Priority register (IP) and the Timer Control register (TCON). The program can block all or any of the combinations of the interrupt from acting on the program by suitable setting or clearing of these registers. After the interrupts has been handled by the interrupt subroutine, which is placed by the programmer in the interrupt location in the program memory, the interrupt program must resume operation at the instruction where the interrupt take place. Program resumption is done by storing the interrupted PC address on the stack in ram before changing the PC to the interrupt address in ROM. The PC address will be stored from the stack after an RETI instruction is executed at the end of the interrupt subroutine.