01-01-2013, 04:28 PM
8051 INTERFACING TO EXTERNAL MEMORY
[attachment=46058]
Memory Address Decoding
The processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip.
In order to splice a memory device into the address space of the processor, decoding is necessary.
For example, the 8088 issues 20‐bit addresses for a total of 1MB of memory address space. However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins.
A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section of the 1MB address space
Basic types of address decoding
Exhaustive — 1:1 mapping of unique addresses to one hardware register (physical memory location)
2. Partial — n:1 mapping of n unique addresses to one hardware register.
Partial decoding allows a memory location to have more than one address, allowing the programmer to reference a memory location using n different addresses.
It may also be done just to simplify the decoding hardware, when not all of the CPU's address space is needed.
Synonyms: Foldback, multiply mapped, partially mapped.
3. Linear — Address lines are used directly without any decoding logic.
This is done with devices such as RAMs and ROMs that have a sequence of address inputs, and with peripheral chips that have a similar sequence of inputs for addressing a bank of registers.
Linear addressing is rarely used alone (only when there are few devices on the bus, as using purely linear addressing for more than one device usually wastes a lot of address space)
Combined with one of the other methods to select a device or group of devices within which the linear addressing selects a single register or memory location.
Incomplete address decoding
Addresses may be decoded completely or incompletely by a device.
Complete decoding involves checking every line of the address bus, causing an open data bus when the CPU accesses an unmapped region of memory.
(Note that even with incomplete decoding, decoded partial regions may not be associated with any device, leaving the data bus open when those regions are accessed.)
Incomplete decoding, or partial decoding, uses simpler and often cheaper logic that examines only some address lines.
Such simple decoding circuitry might allow a device to respond to several different addresses, effectively creating virtual copies of the device at different places in the memory map.
All of these copies refer to the same real device, so there is no particular advantage in doing this, except to simplify the decoder (or possibly the software that uses the device).
This is also known as address aliasing; Aliasing has other meanings in computing. Commonly, the decoding itself is programmable, so the system can reconfigure its own memory map as required, though this is a newer development and generally in conflict with the intent of being cheaper.
[attachment=46058]
Memory Address Decoding
The processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip.
In order to splice a memory device into the address space of the processor, decoding is necessary.
For example, the 8088 issues 20‐bit addresses for a total of 1MB of memory address space. However, the BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins.
A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section of the 1MB address space
Basic types of address decoding
Exhaustive — 1:1 mapping of unique addresses to one hardware register (physical memory location)
2. Partial — n:1 mapping of n unique addresses to one hardware register.
Partial decoding allows a memory location to have more than one address, allowing the programmer to reference a memory location using n different addresses.
It may also be done just to simplify the decoding hardware, when not all of the CPU's address space is needed.
Synonyms: Foldback, multiply mapped, partially mapped.
3. Linear — Address lines are used directly without any decoding logic.
This is done with devices such as RAMs and ROMs that have a sequence of address inputs, and with peripheral chips that have a similar sequence of inputs for addressing a bank of registers.
Linear addressing is rarely used alone (only when there are few devices on the bus, as using purely linear addressing for more than one device usually wastes a lot of address space)
Combined with one of the other methods to select a device or group of devices within which the linear addressing selects a single register or memory location.
Incomplete address decoding
Addresses may be decoded completely or incompletely by a device.
Complete decoding involves checking every line of the address bus, causing an open data bus when the CPU accesses an unmapped region of memory.
(Note that even with incomplete decoding, decoded partial regions may not be associated with any device, leaving the data bus open when those regions are accessed.)
Incomplete decoding, or partial decoding, uses simpler and often cheaper logic that examines only some address lines.
Such simple decoding circuitry might allow a device to respond to several different addresses, effectively creating virtual copies of the device at different places in the memory map.
All of these copies refer to the same real device, so there is no particular advantage in doing this, except to simplify the decoder (or possibly the software that uses the device).
This is also known as address aliasing; Aliasing has other meanings in computing. Commonly, the decoding itself is programmable, so the system can reconfigure its own memory map as required, though this is a newer development and generally in conflict with the intent of being cheaper.