02-01-2013, 11:54 AM
Interrupts of 8051
[attachment=46115]
Interrupts
An interrupt is the occurrence of a condition--an event -- that cause a temporary suspension of a program while the event is serviced by another program (Interrupt Service Routine ISR or Interrupt Handler).
Interrupt-Driven System-- gives the illusion of doing many things simultaneously, quick response to events, suitable for real-time control application.
Base level--interrupted program, foreground.
Interrupt level--ISR, background.
8051 Interrupt Organization
5 interrupt sources: 2 external, 2 timer, a serial port
2 programmable interrupt priority levels
fixed interrupt polling sequence
can be enabled or disabled
IE (A8H), IP (B8H) for controlling interrupts
Polling Sequence
If two interrupts of the same priority occur simultaneously, a fixed polling sequence determines which is serviced first.
The polling sequence is External 0 > Timer 0 > External 1 > Timer 1 > Serial Port > Timer 2
Processing Interrupts
When an interrupt occurs and is accepted by the CPU, the main program is interrupted. The following actions occur:
The current instruction completes execution.
The PC is saved on the stack.
The current interrupt status is saved internally.
Interrupts are blocked at the level of the interrupt.
The PC is loaded with the vector address of the ISR
The ISR executes.
The ISR finishes with an RETI instruction, which retrieves the old value of PC from the stack and restores the old interrupt status. Execution of the main program continues where it left off.
Program Design Using Interrupts
I/O event handling:
Polling: main program keeps checking the flag, waiting for the occurrence of the event. Inefficient in some cases.
Interrupt-driven: CPU can handle other things without wasting time waiting for the event. Efficient, prompt if ISR is not so complex. Suitable for control application.
I/O processor: dedicated processor to handle most of the I/O job without CPU intervention. Best but most expensive.
Serial Port Interrupts
SPISR must check RI or TI and clears it.
TI occurs at the end of the 8th bit time in mode 0 or at the beginning of stop bit in the other modes. Must be cleared by software.
RI occurs at the end of the 8th bit time in mode 0 or half way through the stop bit in other modes when SM2 =0. If SM2 = 1, RI = RB8 in mode 2,3 and RI = 1 only if valid stop bit is received in mode 1.
[attachment=46115]
Interrupts
An interrupt is the occurrence of a condition--an event -- that cause a temporary suspension of a program while the event is serviced by another program (Interrupt Service Routine ISR or Interrupt Handler).
Interrupt-Driven System-- gives the illusion of doing many things simultaneously, quick response to events, suitable for real-time control application.
Base level--interrupted program, foreground.
Interrupt level--ISR, background.
8051 Interrupt Organization
5 interrupt sources: 2 external, 2 timer, a serial port
2 programmable interrupt priority levels
fixed interrupt polling sequence
can be enabled or disabled
IE (A8H), IP (B8H) for controlling interrupts
Polling Sequence
If two interrupts of the same priority occur simultaneously, a fixed polling sequence determines which is serviced first.
The polling sequence is External 0 > Timer 0 > External 1 > Timer 1 > Serial Port > Timer 2
Processing Interrupts
When an interrupt occurs and is accepted by the CPU, the main program is interrupted. The following actions occur:
The current instruction completes execution.
The PC is saved on the stack.
The current interrupt status is saved internally.
Interrupts are blocked at the level of the interrupt.
The PC is loaded with the vector address of the ISR
The ISR executes.
The ISR finishes with an RETI instruction, which retrieves the old value of PC from the stack and restores the old interrupt status. Execution of the main program continues where it left off.
Program Design Using Interrupts
I/O event handling:
Polling: main program keeps checking the flag, waiting for the occurrence of the event. Inefficient in some cases.
Interrupt-driven: CPU can handle other things without wasting time waiting for the event. Efficient, prompt if ISR is not so complex. Suitable for control application.
I/O processor: dedicated processor to handle most of the I/O job without CPU intervention. Best but most expensive.
Serial Port Interrupts
SPISR must check RI or TI and clears it.
TI occurs at the end of the 8th bit time in mode 0 or at the beginning of stop bit in the other modes. Must be cleared by software.
RI occurs at the end of the 8th bit time in mode 0 or half way through the stop bit in other modes when SM2 =0. If SM2 = 1, RI = RB8 in mode 2,3 and RI = 1 only if valid stop bit is received in mode 1.