02-01-2013, 03:02 PM
G.NAVEEN REDDY
[attachment=46195]
Career Objective:
To pursue a successful career in the field of VLSI Design and Verification, by continuously learning new technologies and using those to enable the organization achieve its goals.
WORK EXPERTISE BRIEF
• Good understanding of ASIC verification flow.
• Good programming skills in Verilog Hardware Description Languages (HDL) .Hands on experience with EDA tools ( RivieraPRO, Questasim,modelsim,).
• Good Understanding of HVL concepts. Able to code test scenario using existing given test plan. Knowledge of HVL test bench components.
Projects:
1. Verification of AMBA 3.0 Advanced Hi-Speed Bus [AHB -Lite]
Tools Used : Questa Sim
Language Used: Verilog
Description:
AMBA AHB-Lite addresses the requirements of high-performance synthesizable designs. It is a bus interface that supports a single bus master and provides high-bandwidth operation. AHB-Lite implements the features required for high-performance, high clock frequency systems including:
• Burst transfers
• Single-clock edge operation
• Wide data bus configurations, 64, 128, 256, 512, and 1024 bits.
Technical Skills:
HDL : Verilog
HVL : System verilog,system verilog assertions,uvm
Simulation Tools : Modelsim, Riviera-Pro, Questasim, Cadence
(NCsim), VCS, Mpsim
Operating Systems : Windows, Linux
Scripting Language : Make file.
Educational Qualification:
MS (VLSI CAD) (CGPA6.5 till 3rd semester) 2013
Manipal University, Manipal.
B.E. (ECE) (1st class with 65%) 2011
S.V. College of Engineering and Technology, JNTU Hyderabad.
Intermediate (1st class with 72%) 2007
Nagarjuna Junior College, Nandyal, A.P.
Tenth class (1st class with 72%) 2005
Nalanda Residential School, Nandyal, A.P.
[attachment=46195]
Career Objective:
To pursue a successful career in the field of VLSI Design and Verification, by continuously learning new technologies and using those to enable the organization achieve its goals.
WORK EXPERTISE BRIEF
• Good understanding of ASIC verification flow.
• Good programming skills in Verilog Hardware Description Languages (HDL) .Hands on experience with EDA tools ( RivieraPRO, Questasim,modelsim,).
• Good Understanding of HVL concepts. Able to code test scenario using existing given test plan. Knowledge of HVL test bench components.
Projects:
1. Verification of AMBA 3.0 Advanced Hi-Speed Bus [AHB -Lite]
Tools Used : Questa Sim
Language Used: Verilog
Description:
AMBA AHB-Lite addresses the requirements of high-performance synthesizable designs. It is a bus interface that supports a single bus master and provides high-bandwidth operation. AHB-Lite implements the features required for high-performance, high clock frequency systems including:
• Burst transfers
• Single-clock edge operation
• Wide data bus configurations, 64, 128, 256, 512, and 1024 bits.
Technical Skills:
HDL : Verilog
HVL : System verilog,system verilog assertions,uvm
Simulation Tools : Modelsim, Riviera-Pro, Questasim, Cadence
(NCsim), VCS, Mpsim
Operating Systems : Windows, Linux
Scripting Language : Make file.
Educational Qualification:
MS (VLSI CAD) (CGPA6.5 till 3rd semester) 2013
Manipal University, Manipal.
B.E. (ECE) (1st class with 65%) 2011
S.V. College of Engineering and Technology, JNTU Hyderabad.
Intermediate (1st class with 72%) 2007
Nagarjuna Junior College, Nandyal, A.P.
Tenth class (1st class with 72%) 2005
Nalanda Residential School, Nandyal, A.P.