05-01-2013, 04:29 PM
Design for Testability in Digital Integrated circuits
[attachment=46580]
Introduction and Objectives
This course provides an introductory text on testability of Digital ASIC devices. The aim
of the course is to introduce the student to various techniques which are designed to
reduce the amount of input test patterns required to ensure that an acceptable level of
fault coverage has been obtained.
Testability In Digital Systems
Being able to design a workable system solution for a given problem is only half the
battle unfortunately. We must also be able to test the system to a degree which ensures
that we can have a high confidence level that it is fully functional. This is generally not a
straightforward task, in very small scale digital systems, we can test exhaustively, that is
to say, we can exercise the system over its full range of operating conditions. In a larger
scale system, it is no longer possible to do this and therefore we must look at other
strategies to ensure that the system will be properly tested.
When testing a digital logic device, we apply a stimulus to the inputs of the device and
check its response to establish that it is performing correctly. The input stimulus is
referred to as a test pattern.
In general, we observe the response of the device at its normal output pins, however, it
may be that the device is specially configured during the test, to permit us to observe
some internal nodes which generally would not be accessible to the user.
The response of the device is evaluated by comparing it to an expected response which
may be generated by measuring the response of a known good device, or by simulation
on the computer.
If the device under test (DUT) passes the test, we cannot say categorically that it is a
``good'' device.
The only conclusion that we can draw from the device passing a test, is that the device
does not contain any of the faults for which it was tested. It is important to grasp this
point, a device may contain a huge number of potential faults, some of which may even
mask each other under specified operating conditions. The designer can only be sure that
the device is 100%good if it has been 100%tested, this is rarely possible in real life
systems.
Faults
What type of faults are we trying to detect ? We are starting with the assumption that
logically, the system performs its desired function, and that any faults occuring will be
due to electrical problems associated with one or more of its component parts.
Two key concepts are of interest here, these are :
· Controllability
· Observability
During the design of a system, the designer must ensure that the test engineers have the
means to set or reset key nodes in the system, that is, to control them. Equally as
important is the requirement that the response to this control will be observable, that is,
that we will be able to see clearly the effects of the test patterns applied.
1. Controllability - Being able to set up known internal states.
2. Combinatorial Testability - Being able to generate all states to fully exercise all
combinations of circuit states.
3. Observability - Being able to observe the effects of a state change as it occurs
(preferably at the system primary outputs).
Test Vector Generation
In VLSI circuits, we have a high ratio of logic gates to pins on the device, there is
generally no way of accessing most of the logic, so we cannot directly probe the internals
of the device. Because of this problem, we need a way of generating tests which, when
applied to the inputs of a circuit, give a set of signals which indicate whether or not the
device is good or faulty. The set of stimulus input and expected output pattern is called a
``Test Vector''. The test vectors distinguish between the good machine and the faulted
machine. Figure 1 shows a digital device, as we can see, there is only access to the
primary inputs and outputs, and therefore the device must be tested using only these
ports.
[attachment=46580]
Introduction and Objectives
This course provides an introductory text on testability of Digital ASIC devices. The aim
of the course is to introduce the student to various techniques which are designed to
reduce the amount of input test patterns required to ensure that an acceptable level of
fault coverage has been obtained.
Testability In Digital Systems
Being able to design a workable system solution for a given problem is only half the
battle unfortunately. We must also be able to test the system to a degree which ensures
that we can have a high confidence level that it is fully functional. This is generally not a
straightforward task, in very small scale digital systems, we can test exhaustively, that is
to say, we can exercise the system over its full range of operating conditions. In a larger
scale system, it is no longer possible to do this and therefore we must look at other
strategies to ensure that the system will be properly tested.
When testing a digital logic device, we apply a stimulus to the inputs of the device and
check its response to establish that it is performing correctly. The input stimulus is
referred to as a test pattern.
In general, we observe the response of the device at its normal output pins, however, it
may be that the device is specially configured during the test, to permit us to observe
some internal nodes which generally would not be accessible to the user.
The response of the device is evaluated by comparing it to an expected response which
may be generated by measuring the response of a known good device, or by simulation
on the computer.
If the device under test (DUT) passes the test, we cannot say categorically that it is a
``good'' device.
The only conclusion that we can draw from the device passing a test, is that the device
does not contain any of the faults for which it was tested. It is important to grasp this
point, a device may contain a huge number of potential faults, some of which may even
mask each other under specified operating conditions. The designer can only be sure that
the device is 100%good if it has been 100%tested, this is rarely possible in real life
systems.
Faults
What type of faults are we trying to detect ? We are starting with the assumption that
logically, the system performs its desired function, and that any faults occuring will be
due to electrical problems associated with one or more of its component parts.
Two key concepts are of interest here, these are :
· Controllability
· Observability
During the design of a system, the designer must ensure that the test engineers have the
means to set or reset key nodes in the system, that is, to control them. Equally as
important is the requirement that the response to this control will be observable, that is,
that we will be able to see clearly the effects of the test patterns applied.
1. Controllability - Being able to set up known internal states.
2. Combinatorial Testability - Being able to generate all states to fully exercise all
combinations of circuit states.
3. Observability - Being able to observe the effects of a state change as it occurs
(preferably at the system primary outputs).
Test Vector Generation
In VLSI circuits, we have a high ratio of logic gates to pins on the device, there is
generally no way of accessing most of the logic, so we cannot directly probe the internals
of the device. Because of this problem, we need a way of generating tests which, when
applied to the inputs of a circuit, give a set of signals which indicate whether or not the
device is good or faulty. The set of stimulus input and expected output pattern is called a
``Test Vector''. The test vectors distinguish between the good machine and the faulted
machine. Figure 1 shows a digital device, as we can see, there is only access to the
primary inputs and outputs, and therefore the device must be tested using only these
ports.