14-01-2013, 03:18 PM
KRISHNA CHAITANYA KATHARI
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OBJECTIVE
Seeking a challenging position in the field of VLSI design where I can utilize my technical knowledge and expertise to make a significant contribution towards the organizational growth.
EDUCATION
Master of Science in Electrical and Computer Engineering Jan 2011 – Dec 2012
Southern Illinois University, Edwardsville, Illinois, USA Current GPA: 3.7/4.0
Bachelor in Electronics & Communication Engineering Sep 2006 – May 2010
Jawaharlal Nehru Technological University, Hyderabad, India GPA: 3.6/4.0
Coursework: VLSI/CAD Design, CMOS Analog Integrated Circuits, Computer Architecture and organization, Mixed – Design and modelling, High performance architectures, Computer and Network Security, Digital Image Processing, Electronic Circuits and a Master’s Project.
TECHNICAL SKILLS
• Operating Systems : Windows 2000/XP/Vista/windows 7, Linux and UNIX
• Programming Languages : C, C++, Matlab
• Hardware Languages : Verilog HDL, VHDL, Verilog AMS and System Verilog
• Microsoft Packages : Microsoft Office 2007
• Designing Tools : TopSpice 8 Circuit Simulator, Computer Vision and Image
Processing (CVIP) Tools, CAD tools which include Cadence schematic editor – Composer, Layout editor – Virtuoso, Simulator – Spectre, Waveform viewer – Simvision, NC Verilog, Modelsim and Xilinx ISE.
PROFESSIONAL PROFILE
• Accomplished Electrical Engineering professional with hands on experience in VerilogA, Verilog, VHDL, VLSI/CAD, TopSpice 8 and Matlab.
• Strong background in VLSI/CHIP design and Skilled in creating schematics for RTL, schematic capture, floor planning, Place-and-route, timing closure, Verification and simulation using the virtuoso analog design environment.
• Expertise in handling Layout design, Layout Vs Schematic check and Post- Layout simulation.
• Familiar with the Cadence Analog mixed signal analyzer (AMS) and LabVIEW Software.
• Strong knowledge on Ethernet protocol.
• Individual with self motivation and is comfortable working in a diverse team environment.
PROFESSIONAL EXPERIENCE
Southern Illinois University, Edwardsville Jan 2012 - Present
Teaching Assistant under Dr. George L. Engel
• Spring 2012: Guided students through the use of TopSpice Simulator for three different Electronics projects and helped them to practically demo their circuit on the Breadboard.
• Fall 2012(Current semester): Guiding students through the Cadence IC design schematic capture, Simulation using Spectre, Layout and Extraction, LVS and Post – Layout Simulation.
[attachment=46840]
OBJECTIVE
Seeking a challenging position in the field of VLSI design where I can utilize my technical knowledge and expertise to make a significant contribution towards the organizational growth.
EDUCATION
Master of Science in Electrical and Computer Engineering Jan 2011 – Dec 2012
Southern Illinois University, Edwardsville, Illinois, USA Current GPA: 3.7/4.0
Bachelor in Electronics & Communication Engineering Sep 2006 – May 2010
Jawaharlal Nehru Technological University, Hyderabad, India GPA: 3.6/4.0
Coursework: VLSI/CAD Design, CMOS Analog Integrated Circuits, Computer Architecture and organization, Mixed – Design and modelling, High performance architectures, Computer and Network Security, Digital Image Processing, Electronic Circuits and a Master’s Project.
TECHNICAL SKILLS
• Operating Systems : Windows 2000/XP/Vista/windows 7, Linux and UNIX
• Programming Languages : C, C++, Matlab
• Hardware Languages : Verilog HDL, VHDL, Verilog AMS and System Verilog
• Microsoft Packages : Microsoft Office 2007
• Designing Tools : TopSpice 8 Circuit Simulator, Computer Vision and Image
Processing (CVIP) Tools, CAD tools which include Cadence schematic editor – Composer, Layout editor – Virtuoso, Simulator – Spectre, Waveform viewer – Simvision, NC Verilog, Modelsim and Xilinx ISE.
PROFESSIONAL PROFILE
• Accomplished Electrical Engineering professional with hands on experience in VerilogA, Verilog, VHDL, VLSI/CAD, TopSpice 8 and Matlab.
• Strong background in VLSI/CHIP design and Skilled in creating schematics for RTL, schematic capture, floor planning, Place-and-route, timing closure, Verification and simulation using the virtuoso analog design environment.
• Expertise in handling Layout design, Layout Vs Schematic check and Post- Layout simulation.
• Familiar with the Cadence Analog mixed signal analyzer (AMS) and LabVIEW Software.
• Strong knowledge on Ethernet protocol.
• Individual with self motivation and is comfortable working in a diverse team environment.
PROFESSIONAL EXPERIENCE
Southern Illinois University, Edwardsville Jan 2012 - Present
Teaching Assistant under Dr. George L. Engel
• Spring 2012: Guided students through the use of TopSpice Simulator for three different Electronics projects and helped them to practically demo their circuit on the Breadboard.
• Fall 2012(Current semester): Guiding students through the Cadence IC design schematic capture, Simulation using Spectre, Layout and Extraction, LVS and Post – Layout Simulation.