16-01-2013, 03:19 PM
The 80386 Microprocessor
[attachment=47191]
INTRODUCTION
The 80386 includes a Bus Interface Unit for reading and providing data and instructions,
witha Prefetch Queue, an IU for controlling the EU with its registers, as well as an AU for
generating memory and I/O addresses
The features of the 80386 are:
• 32-bit general and offset registers
• 16-byte prefetch queue
• Memory Management Unit with a Segmentation Unit and a Paging Unit
• 32-bit Address and Data Bus
• 4-Gbyte Physical address space
• 64-Tbyte virtual address space
• i387 numerical coprocessor with IEEE standard-754-1985 for floating point arithmetic
• 64K 8-, 16-, or 32-bit ports
• Implementation of real, protected and virtual 8086 modes
Some of the elements that help to give the 80386 a performance improvement over earlier generation
processors are its expanded bus width, its prefetch queue, its numeric coprocessor and its generally
improved instruction set.
80386 OPERATING MODES
The 80386 and the Pentium support three operating modes: protected mode, real-address mode, and
system management mode. We’ll discuss these when we talk about the Pentium.
Stack Segment and Stack Pointer
Usually every program has its own stack segment. As on the 8086 the stack grows downwards, that is,
the value of the stack pointer decreases with a PUSH instruction and increases with a POP instruction. In
the i386, if data is stored on the stack the value of ESP is reduced by 4, because the i386 always writes a
complete double word (2*16 bits = 4*8 bits). When the i386 operates in 16-bit mode, only 2 bytes are
written to the stack, and the value of SP is only reduced by 2, with each push.
Data Segments.
The i386 adds two more data segment registers, called FS and GS.
The i386 has four control registers and four memory mangement registers for protected mode, as well as
8 debug registers. These registers are particularly useful in a multitasking environment. The debug
registers can be useful in locating errors in a given task.
Instruction Pipelining
The main reason for pipelining instructions is that it allows some operations to be carried out in parallel.
Let’s look at our Fetch-Decode-Execute model in a little more detail. These are the steps that need to be
carried out when a microprocessor executes an instruction:
• Read the instruction from memory or the prefetch queue (instruction fetch phase)
• Decode the instruction (decode phase)
• Where necessary, fetch the operands (operand fetch phase)
• Execute the instruction (execute phase)
• Write back the result (write-back phase)
SOFTWARE IMPLICATIONS OF RISC ARCHITECTURES
Compiler issues.
To get the most out of a RISC architecture, you need to use a good optimising compiler that is very aware
of the features of the processor at which it is targeted. The compilers, being aware of the pipeline issues
in the processors can achieve optimal performance. Often the processor instruction set may be defined in
association with the compiler writers.
Code Density.
RISC processors use sequences of simple instructions to do the same thing as a single powerful CISC
instruction so compiled programs for RISC processors tend to be longer and use more memory than
similar programs for CISC processors. For example, similar programs compiled for a Pentium and a
PowerPC take typically 30% more code memory for the PowerPC version than for the Pentium. This point
may be a consideration in applications where memory is limited, such as in some embedded systems.
[attachment=47191]
INTRODUCTION
The 80386 includes a Bus Interface Unit for reading and providing data and instructions,
witha Prefetch Queue, an IU for controlling the EU with its registers, as well as an AU for
generating memory and I/O addresses
The features of the 80386 are:
• 32-bit general and offset registers
• 16-byte prefetch queue
• Memory Management Unit with a Segmentation Unit and a Paging Unit
• 32-bit Address and Data Bus
• 4-Gbyte Physical address space
• 64-Tbyte virtual address space
• i387 numerical coprocessor with IEEE standard-754-1985 for floating point arithmetic
• 64K 8-, 16-, or 32-bit ports
• Implementation of real, protected and virtual 8086 modes
Some of the elements that help to give the 80386 a performance improvement over earlier generation
processors are its expanded bus width, its prefetch queue, its numeric coprocessor and its generally
improved instruction set.
80386 OPERATING MODES
The 80386 and the Pentium support three operating modes: protected mode, real-address mode, and
system management mode. We’ll discuss these when we talk about the Pentium.
Stack Segment and Stack Pointer
Usually every program has its own stack segment. As on the 8086 the stack grows downwards, that is,
the value of the stack pointer decreases with a PUSH instruction and increases with a POP instruction. In
the i386, if data is stored on the stack the value of ESP is reduced by 4, because the i386 always writes a
complete double word (2*16 bits = 4*8 bits). When the i386 operates in 16-bit mode, only 2 bytes are
written to the stack, and the value of SP is only reduced by 2, with each push.
Data Segments.
The i386 adds two more data segment registers, called FS and GS.
The i386 has four control registers and four memory mangement registers for protected mode, as well as
8 debug registers. These registers are particularly useful in a multitasking environment. The debug
registers can be useful in locating errors in a given task.
Instruction Pipelining
The main reason for pipelining instructions is that it allows some operations to be carried out in parallel.
Let’s look at our Fetch-Decode-Execute model in a little more detail. These are the steps that need to be
carried out when a microprocessor executes an instruction:
• Read the instruction from memory or the prefetch queue (instruction fetch phase)
• Decode the instruction (decode phase)
• Where necessary, fetch the operands (operand fetch phase)
• Execute the instruction (execute phase)
• Write back the result (write-back phase)
SOFTWARE IMPLICATIONS OF RISC ARCHITECTURES
Compiler issues.
To get the most out of a RISC architecture, you need to use a good optimising compiler that is very aware
of the features of the processor at which it is targeted. The compilers, being aware of the pipeline issues
in the processors can achieve optimal performance. Often the processor instruction set may be defined in
association with the compiler writers.
Code Density.
RISC processors use sequences of simple instructions to do the same thing as a single powerful CISC
instruction so compiled programs for RISC processors tend to be longer and use more memory than
similar programs for CISC processors. For example, similar programs compiled for a Pentium and a
PowerPC take typically 30% more code memory for the PowerPC version than for the Pentium. This point
may be a consideration in applications where memory is limited, such as in some embedded systems.