16-01-2013, 03:22 PM
VLSI Design and Validation
[attachment=47205]
What is RTL Design
Register Transfer Level modeling is a Hardware Design Language design of behaviors that are bounded by the period of a clock.
Within a clock period, functions are evaluated and can pass the results of these to further functions. The only way to convey information into another clock cycle is via a register.
Within each cycle, statements can be concurrent or sequentially ordered.
Describing the structure & behavior of a product, addressing its design, verification, and synthesis
How the product will behave if it is implemented flawlessly
Main RTL Design Flows
Dynamic Validation using simulation
Compile the model into C, generate tests & run
Static Analysis
Check design rules, analyze model timing (clocking)
Formal Verification - Equivalence & properties
Comparing two models (RTL or schematics)
Verifying properties on the model
Synthesis flow
Deriving optimized circuits and Physical Designs
Design For Testability
Inserting & verifying scan-latches at the RTL level
Estimation: Power, timing? Area?
Estimation of expected power usage
Timing/Area flows used in the past but EOLed. Future?
The VHDL language, syntax and semantics
VHSIC (Very High Speed IC) HDL was developed to be the ultimate language
Supports multiple implementations of the same box
Supports any user-defined data types
Well accepted in Europe, less in US
Very complex language, allowing many styles of design
As a result, an official “synthesizable subset” has become the real language being used
Types of problems in CAD
Mathematically, most CAD tools address combinatorial decision and optimization problems
Decision problems have a binary (true or false) solution
e.g. Are these 2 functions equivalent?
Optimization problems are targeted to finding a minimum cost solution
e.g. Find a minimum delay logic implementation of a function
Most of these problems are intractable (NP-hard or NP-complete)
Exact algorithms are of exponential complexity or higher
Must use heuristics (approximation algorithms) to get inexact but practical solutions, using reasonable computer time and memory
[attachment=47205]
What is RTL Design
Register Transfer Level modeling is a Hardware Design Language design of behaviors that are bounded by the period of a clock.
Within a clock period, functions are evaluated and can pass the results of these to further functions. The only way to convey information into another clock cycle is via a register.
Within each cycle, statements can be concurrent or sequentially ordered.
Describing the structure & behavior of a product, addressing its design, verification, and synthesis
How the product will behave if it is implemented flawlessly
Main RTL Design Flows
Dynamic Validation using simulation
Compile the model into C, generate tests & run
Static Analysis
Check design rules, analyze model timing (clocking)
Formal Verification - Equivalence & properties
Comparing two models (RTL or schematics)
Verifying properties on the model
Synthesis flow
Deriving optimized circuits and Physical Designs
Design For Testability
Inserting & verifying scan-latches at the RTL level
Estimation: Power, timing? Area?
Estimation of expected power usage
Timing/Area flows used in the past but EOLed. Future?
The VHDL language, syntax and semantics
VHSIC (Very High Speed IC) HDL was developed to be the ultimate language
Supports multiple implementations of the same box
Supports any user-defined data types
Well accepted in Europe, less in US
Very complex language, allowing many styles of design
As a result, an official “synthesizable subset” has become the real language being used
Types of problems in CAD
Mathematically, most CAD tools address combinatorial decision and optimization problems
Decision problems have a binary (true or false) solution
e.g. Are these 2 functions equivalent?
Optimization problems are targeted to finding a minimum cost solution
e.g. Find a minimum delay logic implementation of a function
Most of these problems are intractable (NP-hard or NP-complete)
Exact algorithms are of exponential complexity or higher
Must use heuristics (approximation algorithms) to get inexact but practical solutions, using reasonable computer time and memory