18-01-2013, 04:13 PM
8086 PINS and SIGNALS
[attachment=47578]
INTRODUCTION
The 8086 pins and signals are shown below. Unless otherwise indicated, all 8086 pins are TTL compatible. The 8086 can operate in two modes. These are minimum mode (uniprocessor system – single 8086) and maximum mode (multiprocessor system system – more than one 8086 or other 8088). Pin Descriptions for the 8086 is given below:
1. MN/MX is an input pin used to select one of these modes. When MN/MX is HIGH, the 8086 operates in the minimum mode. When MN/MX is LOW, 8086 is configured to support multiprocessor systems. In this case, the Intel 8288 bus controller is added to the 8086 to provide bus controls.
2. Pins 2 through 16 and 39 (AD15 - AD0) are a 16-bit multiplexed address/data bus. During the first clock cycle AD0-AD15 are the low order 16 bits of address. The 8086 have a total of 20 address lines. The upper four lines (35 – 38)are multiplexed with the status signals for the 8086. These are the A16/S3, A17/S4, A18/S5, and A19/S6. During the first clock period of a bus cycle, the entire 20-bit address is available on these lines. During all other clock cycles for memory and I/O operations, AD15-AD0 contains the 16-bit data, and S3, S4, S5, and S6 become status lines. S3 and S4 lines are decoded as follows:
Status bits S3 and S4 indicate the segment register that is being used to generate the address the address and bit S5 reflects the contents of the IF flag. S6 is always held at 0 and indicates that an 8086 is controlling the system bus.
3. Pins 1 and 20 are grounded. Pin 17 is NMI. This is the Non-Maskable Interrupt input activated by a leading edge. Pin 18 is INTR. INTR is the maskable interrupt input. Pin 19 is CLK is for supplying the clock signal that synchronizes the activity within the CPU.
Pin 21 (RESET) is the system reset input signal. When the 8086 detects the positive going edge of a pulse on RESET, it stops all activities until the signal goes LOW.
[attachment=47578]
INTRODUCTION
The 8086 pins and signals are shown below. Unless otherwise indicated, all 8086 pins are TTL compatible. The 8086 can operate in two modes. These are minimum mode (uniprocessor system – single 8086) and maximum mode (multiprocessor system system – more than one 8086 or other 8088). Pin Descriptions for the 8086 is given below:
1. MN/MX is an input pin used to select one of these modes. When MN/MX is HIGH, the 8086 operates in the minimum mode. When MN/MX is LOW, 8086 is configured to support multiprocessor systems. In this case, the Intel 8288 bus controller is added to the 8086 to provide bus controls.
2. Pins 2 through 16 and 39 (AD15 - AD0) are a 16-bit multiplexed address/data bus. During the first clock cycle AD0-AD15 are the low order 16 bits of address. The 8086 have a total of 20 address lines. The upper four lines (35 – 38)are multiplexed with the status signals for the 8086. These are the A16/S3, A17/S4, A18/S5, and A19/S6. During the first clock period of a bus cycle, the entire 20-bit address is available on these lines. During all other clock cycles for memory and I/O operations, AD15-AD0 contains the 16-bit data, and S3, S4, S5, and S6 become status lines. S3 and S4 lines are decoded as follows:
Status bits S3 and S4 indicate the segment register that is being used to generate the address the address and bit S5 reflects the contents of the IF flag. S6 is always held at 0 and indicates that an 8086 is controlling the system bus.
3. Pins 1 and 20 are grounded. Pin 17 is NMI. This is the Non-Maskable Interrupt input activated by a leading edge. Pin 18 is INTR. INTR is the maskable interrupt input. Pin 19 is CLK is for supplying the clock signal that synchronizes the activity within the CPU.
Pin 21 (RESET) is the system reset input signal. When the 8086 detects the positive going edge of a pulse on RESET, it stops all activities until the signal goes LOW.