21-01-2013, 12:02 PM
Influence of channel width on n- and p-type nano-wire-MOSFETs on silicon on insulator substrate
[attachment=47845]
Abstract
The fabrication and characterization of nanoscale n- and p-type multi-wire metal–oxide semiconductor field
effect transistors (MOSFETs) with a triple gate structure on silicon-on-insulator material (SOI) is described in
this paper. Experimental results are compared to simulation with special emphasis on the influence of channel
width on the subthreshold behavior. Experiment and simulation show that the threshold voltage depends strongly
on the wire width at dimensions below 100 nm. It is further shown that the transition from partial to full channel
depletion is dependent on channel geometry. Finally, an increased on-current per chip area is demonstrated for
triple-gate SOI MOSFETs compared to planar SOI devices.
Introduction
The transition from micro- to nanoscale MOSFETs is the major challenge for the semiconductor
industry during the next decade. Even to reach the 65 nm node, which is expected to be in production
in 2007, simple downscaling of device dimensions may not be sufficient to achieve the ambitious
goals set by the Semiconductor Industry Association (SIA) [1]. Non-classical devices such as dual- or
multi-gate wire-MOSFETs on Silicon on Insulator substrate (SOI) have been proposed [2] and are
currently being investigated as candidates to solve some of the challenges associated with nanoscale
CMOS: control of short channel effects, increase of on-currents and threshold voltage control [3].
Device design and fabrication
Wire MOSFETs are 3-dimensional devices requiring a 3-dimensional definition of feature sizes.
Fig. 1 shows a schematic top view of a conventional and a multi-wire MOSFET on SOI to define the
nomenclature used in this work. Four different wire structures were fabricated where the width of the
wire is changed successively from W 51450 nm to 70 nm. Wire
According to Fig. 1, transistors with W 51450 nm correspond to quasi-conventional SOI- Gate
MOSFETs, while the multi-wire-transistors with W below 90 nm are clearly 3-dimensional Wire
MOSFETs.
For clarity, in Fig. 2 a schematic cross section along a multi-wire MOSFET gate is displayed
including all dimensions relevant for this paper. An effective device channel width is defined as
W 5W 12t . eff Wire Si
In previous work, the transfer characteristics of wire-MOSFETs with undoped channels have been
studied in the sub 100 nm regime [4–6]. There, the reduction of W improves the subthreshold Wire
behavior as the gate control over the channel potential is enhanced and consequently punch-through is
suppressed.
Simulation
In order to predict the influence of W , 3-dimensional device simulations using the software tool Wire
ATLAS [9] have been performed, with design parameters summarized in Table 1. The drift-diffusion
(DD) model has been used to simulate the transfer characteristics. This model is applicable even
though velocity overshoot [10] is not taken into account, because velocity overshoot has virtually no
effect on DC currents at a gate length of L 5100 nm [5]. Tunneling and impact ionization have Gate
not been taken into account
Experimental results
In Fig. 5 is also shown the first experimental V data from n-MOSFET structures (filled triangles) th
with L 5200 nm. Short channel effects (e.g. charge sharing, DIBL, punch-through) are weak in Gate
simulated and experimental structures, so V results can be compared, although gate lengths and drain th
voltages differ. This is demonstrated by the comparison of the simulated threshold voltage of an
L 5200 nm transistor to the 100 nm MOSFET simulations indicated by the hollow triangle in Fig. 5. G
Almost no difference can be observed.
Qualitatively, the experimental data show the same behavior as the simulations predict. The Vth
values drop significantly below a critical width, but they are lower than predicted in the simulation in
the case of W 590 nm and W 570 nm. Obviously, experimental data indicates that the Wire Wire
transition between PD and FD occurs already at a larger width, represented by the low threshold
voltage of the L 590 nm device. This transition can be further observed in the output characteristics G
shown in Fig. 6 for the case of two n-MOSFETs (W 51450 nm/90 nm).While the wide transistor Wire
exhibits the well known ‘kink’-effect [12] typical for PD-devices, the narrow MOSFET (90 nm)
3 shows an FD behavior without kink effect. For a channel doping of N 51e18/ cm a kink effect A
would be expected for both MOSFETs [13]. Its absence in the wire MOSFET is attributed to a lower
3 channel doping than N 51e18/ cm caused by boron out-diffusion from the channel during A
subsequent process steps. This was confirmed by ATHENA process simulations for an n-MOSFET
with L 5200 nm.
Conclusion
MOSFET structures on silicon-on-insulator substrates with channel widths down to 70 nm and
non-planar gate geometries exhibit attractive increase of on-current per chip area. Charge sharing with
non-planar structures leads to a remarkable reduction of V for channel widths of less than 90 nm. th
This effect has a severe impact on CMOS logic design using triple-gate transistors: The benefit of
reduced short channel effects in triple-gate structures can only be utilized, if the width—and thus the
threshold voltage—of the wires can be tightly controlled. The transition between full and partial
depletion is a function of the gate width as demonstrated in the experiments. Compared to
conventional MOSFETs, a significant increase of on-current per chip area was achieved, making
triple-gate transistors potential candidates for future high-performance circuits.
[attachment=47845]
Abstract
The fabrication and characterization of nanoscale n- and p-type multi-wire metal–oxide semiconductor field
effect transistors (MOSFETs) with a triple gate structure on silicon-on-insulator material (SOI) is described in
this paper. Experimental results are compared to simulation with special emphasis on the influence of channel
width on the subthreshold behavior. Experiment and simulation show that the threshold voltage depends strongly
on the wire width at dimensions below 100 nm. It is further shown that the transition from partial to full channel
depletion is dependent on channel geometry. Finally, an increased on-current per chip area is demonstrated for
triple-gate SOI MOSFETs compared to planar SOI devices.
Introduction
The transition from micro- to nanoscale MOSFETs is the major challenge for the semiconductor
industry during the next decade. Even to reach the 65 nm node, which is expected to be in production
in 2007, simple downscaling of device dimensions may not be sufficient to achieve the ambitious
goals set by the Semiconductor Industry Association (SIA) [1]. Non-classical devices such as dual- or
multi-gate wire-MOSFETs on Silicon on Insulator substrate (SOI) have been proposed [2] and are
currently being investigated as candidates to solve some of the challenges associated with nanoscale
CMOS: control of short channel effects, increase of on-currents and threshold voltage control [3].
Device design and fabrication
Wire MOSFETs are 3-dimensional devices requiring a 3-dimensional definition of feature sizes.
Fig. 1 shows a schematic top view of a conventional and a multi-wire MOSFET on SOI to define the
nomenclature used in this work. Four different wire structures were fabricated where the width of the
wire is changed successively from W 51450 nm to 70 nm. Wire
According to Fig. 1, transistors with W 51450 nm correspond to quasi-conventional SOI- Gate
MOSFETs, while the multi-wire-transistors with W below 90 nm are clearly 3-dimensional Wire
MOSFETs.
For clarity, in Fig. 2 a schematic cross section along a multi-wire MOSFET gate is displayed
including all dimensions relevant for this paper. An effective device channel width is defined as
W 5W 12t . eff Wire Si
In previous work, the transfer characteristics of wire-MOSFETs with undoped channels have been
studied in the sub 100 nm regime [4–6]. There, the reduction of W improves the subthreshold Wire
behavior as the gate control over the channel potential is enhanced and consequently punch-through is
suppressed.
Simulation
In order to predict the influence of W , 3-dimensional device simulations using the software tool Wire
ATLAS [9] have been performed, with design parameters summarized in Table 1. The drift-diffusion
(DD) model has been used to simulate the transfer characteristics. This model is applicable even
though velocity overshoot [10] is not taken into account, because velocity overshoot has virtually no
effect on DC currents at a gate length of L 5100 nm [5]. Tunneling and impact ionization have Gate
not been taken into account
Experimental results
In Fig. 5 is also shown the first experimental V data from n-MOSFET structures (filled triangles) th
with L 5200 nm. Short channel effects (e.g. charge sharing, DIBL, punch-through) are weak in Gate
simulated and experimental structures, so V results can be compared, although gate lengths and drain th
voltages differ. This is demonstrated by the comparison of the simulated threshold voltage of an
L 5200 nm transistor to the 100 nm MOSFET simulations indicated by the hollow triangle in Fig. 5. G
Almost no difference can be observed.
Qualitatively, the experimental data show the same behavior as the simulations predict. The Vth
values drop significantly below a critical width, but they are lower than predicted in the simulation in
the case of W 590 nm and W 570 nm. Obviously, experimental data indicates that the Wire Wire
transition between PD and FD occurs already at a larger width, represented by the low threshold
voltage of the L 590 nm device. This transition can be further observed in the output characteristics G
shown in Fig. 6 for the case of two n-MOSFETs (W 51450 nm/90 nm).While the wide transistor Wire
exhibits the well known ‘kink’-effect [12] typical for PD-devices, the narrow MOSFET (90 nm)
3 shows an FD behavior without kink effect. For a channel doping of N 51e18/ cm a kink effect A
would be expected for both MOSFETs [13]. Its absence in the wire MOSFET is attributed to a lower
3 channel doping than N 51e18/ cm caused by boron out-diffusion from the channel during A
subsequent process steps. This was confirmed by ATHENA process simulations for an n-MOSFET
with L 5200 nm.
Conclusion
MOSFET structures on silicon-on-insulator substrates with channel widths down to 70 nm and
non-planar gate geometries exhibit attractive increase of on-current per chip area. Charge sharing with
non-planar structures leads to a remarkable reduction of V for channel widths of less than 90 nm. th
This effect has a severe impact on CMOS logic design using triple-gate transistors: The benefit of
reduced short channel effects in triple-gate structures can only be utilized, if the width—and thus the
threshold voltage—of the wires can be tightly controlled. The transition between full and partial
depletion is a function of the gate width as demonstrated in the experiments. Compared to
conventional MOSFETs, a significant increase of on-current per chip area was achieved, making
triple-gate transistors potential candidates for future high-performance circuits.