21-01-2013, 03:25 PM
28/40-pin, 8-bit CMOS FLASH Microcontrollers
[attachment=47895]
MEMORY ORGANIZATION
There are two memory blocks in each of these
PICmicro® MCUs. The Program Memory and Data
Memory have separate buses so that concurrent
access can occur and is detailed in this section. The
Program Memory can be read internally by user code
(see Section 3.0).
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual
(DS33023).
Program Memory Organization
The PIC16F7X devices have a 13-bit program counter
capable of addressing an 8K word x 14-bit program
memory space. The PIC16F77/76 devices have
8K words of FLASH program memory and the
PIC16F73/74 devices have 4K words. The program
memory maps for PIC16F7X devices are shown in
Figure 2-1. Accessing a location above the physically
implemented address will cause a wraparound.
The RESET Vector is at 0000h and the Interrupt Vector
is at 0004h.
Data Memory Organization
The Data Memory is partitioned into multiple banks,
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits:
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers
are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
STATUS Register
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bits for
data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC, or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
SSP I2 C Operation
The SSP module in I2C mode, fully implements all slave
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to facilitate
firmware implementations of the master functions.
The SSP module implements the standard mode specifications
as well as 7-bit and 10-bit addressing.
[attachment=47895]
MEMORY ORGANIZATION
There are two memory blocks in each of these
PICmicro® MCUs. The Program Memory and Data
Memory have separate buses so that concurrent
access can occur and is detailed in this section. The
Program Memory can be read internally by user code
(see Section 3.0).
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual
(DS33023).
Program Memory Organization
The PIC16F7X devices have a 13-bit program counter
capable of addressing an 8K word x 14-bit program
memory space. The PIC16F77/76 devices have
8K words of FLASH program memory and the
PIC16F73/74 devices have 4K words. The program
memory maps for PIC16F7X devices are shown in
Figure 2-1. Accessing a location above the physically
implemented address will cause a wraparound.
The RESET Vector is at 0000h and the Interrupt Vector
is at 0004h.
Data Memory Organization
The Data Memory is partitioned into multiple banks,
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits:
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers
are General Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
STATUS Register
The STATUS register contains the arithmetic status of
the ALU, the RESET status and the bank select bits for
data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC, or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable, therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
SSP I2 C Operation
The SSP module in I2C mode, fully implements all slave
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to facilitate
firmware implementations of the master functions.
The SSP module implements the standard mode specifications
as well as 7-bit and 10-bit addressing.