23-01-2013, 10:19 AM
Mealy and Moore Machines
[attachment=48099]
Roth
Analysis of Clocked Sequential Circuits
A Sequential Parity Checker
Analysis by Signal Tracing and Timing Charts
State Tables and Graphs
General Models for Sequential Circuits
Finite State Machines
Thus far, sequential circuit (counter and
register) outputs limited to state variables
In general, sequential circuits (or Finite State
Machines, FSM’s) have outputs in addition to
the state variables
For example, vending machine controllers
generate output signals to dispense product,
provide change, illuminate displays, etc.
Analysis by Signal Tracing and Timing
Diagrams
Timing Analysis
Determine flip-flop input equations
Determine output equations
Mealy or Moore model
Generate timing diagram illustrating circuit’s
response to a particular input sequence
Outputs as well as to state
Mealy Network Example
Timing Diagram and Analysis (cont)
Output transitions occur in response to both input
and state transitions
“glitches” may be generated by transitions in inputs
Moore machines don’t glitch because outputs are
associated with present state only
Assumes gate delays to output(s) much shorter
than clock period
All outputs stable before occurrence of active clock edge
Mealy Machines and Glitches
In synchronous network, glitches don’t matter
All data transfers occur around common, falling
(or rising) clock edge
Register transfer operations
Outputs sampled only on active clock edge
Output is stable before and after active clock edge
Setup and hold times satisfied
FSM Outputs & Timing - Summary
For Moore machine, output is valid after state
transition
Output associated with stable present state
For Mealy machine, output is valid on
occurrence of active clock edge
Output associated with transition from present
state to next state
Output in Mealy machine occurs one clock period
before output in equivalent Moore machine
[attachment=48099]
Roth
Analysis of Clocked Sequential Circuits
A Sequential Parity Checker
Analysis by Signal Tracing and Timing Charts
State Tables and Graphs
General Models for Sequential Circuits
Finite State Machines
Thus far, sequential circuit (counter and
register) outputs limited to state variables
In general, sequential circuits (or Finite State
Machines, FSM’s) have outputs in addition to
the state variables
For example, vending machine controllers
generate output signals to dispense product,
provide change, illuminate displays, etc.
Analysis by Signal Tracing and Timing
Diagrams
Timing Analysis
Determine flip-flop input equations
Determine output equations
Mealy or Moore model
Generate timing diagram illustrating circuit’s
response to a particular input sequence
Outputs as well as to state
Mealy Network Example
Timing Diagram and Analysis (cont)
Output transitions occur in response to both input
and state transitions
“glitches” may be generated by transitions in inputs
Moore machines don’t glitch because outputs are
associated with present state only
Assumes gate delays to output(s) much shorter
than clock period
All outputs stable before occurrence of active clock edge
Mealy Machines and Glitches
In synchronous network, glitches don’t matter
All data transfers occur around common, falling
(or rising) clock edge
Register transfer operations
Outputs sampled only on active clock edge
Output is stable before and after active clock edge
Setup and hold times satisfied
FSM Outputs & Timing - Summary
For Moore machine, output is valid after state
transition
Output associated with stable present state
For Mealy machine, output is valid on
occurrence of active clock edge
Output associated with transition from present
state to next state
Output in Mealy machine occurs one clock period
before output in equivalent Moore machine