23-01-2013, 12:07 PM
Pipelining
[attachment=48142]
Overview
Pipelining is widely used in modern processors.
Pipelining improves system performance in terms of throughput.
Pipelined organization requires sophisticated compilation techniques.
Making the Execution of Programs Faster
Use faster circuit technology to build the processor and the main memory.
Arrange the hardware so that more than one operation can be performed at the same time.
In the latter way, the number of operations performed per second is increased even though the elapsed time needed to perform any one operation is not changed.
Traditional Pipeline Concept
Laundry Example
Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold
Washer takes 30 minutes
Dryer takes 40 minutes
“Folder” takes 20 minutes
Role of Cache Memory
Each pipeline stage is expected to complete in one clock cycle.
The clock period should be long enough to let the slowest pipeline stage to complete.
Faster stages can only wait for the slowest one to complete.
Since main memory is very slow compared to the execution, if each instruction needs to be fetched from main memory, pipeline is almost useless.
Fortunately, we have cache.
Pipeline Performance
The potential increase in performance resulting from pipelining is proportional to the number of pipeline stages.
However, this increase would be achieved only if all pipeline stages require the same time to complete, and there is no interruption throughout program execution.
Unfortunately, this is not true.
SPEEDUP
Consider a k-segment pipeline operating on n data sets. (In the above example, k = 3 and n = 4.)
It takes k clock cycles to fill the pipeline and get the first result from the output of the pipeline.
After that the remaining (n - 1) results will come out at each clock cycle.
It therefore takes (k + n - 1) clock cycles to complete the task.
[attachment=48142]
Overview
Pipelining is widely used in modern processors.
Pipelining improves system performance in terms of throughput.
Pipelined organization requires sophisticated compilation techniques.
Making the Execution of Programs Faster
Use faster circuit technology to build the processor and the main memory.
Arrange the hardware so that more than one operation can be performed at the same time.
In the latter way, the number of operations performed per second is increased even though the elapsed time needed to perform any one operation is not changed.
Traditional Pipeline Concept
Laundry Example
Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold
Washer takes 30 minutes
Dryer takes 40 minutes
“Folder” takes 20 minutes
Role of Cache Memory
Each pipeline stage is expected to complete in one clock cycle.
The clock period should be long enough to let the slowest pipeline stage to complete.
Faster stages can only wait for the slowest one to complete.
Since main memory is very slow compared to the execution, if each instruction needs to be fetched from main memory, pipeline is almost useless.
Fortunately, we have cache.
Pipeline Performance
The potential increase in performance resulting from pipelining is proportional to the number of pipeline stages.
However, this increase would be achieved only if all pipeline stages require the same time to complete, and there is no interruption throughout program execution.
Unfortunately, this is not true.
SPEEDUP
Consider a k-segment pipeline operating on n data sets. (In the above example, k = 3 and n = 4.)
It takes k clock cycles to fill the pipeline and get the first result from the output of the pipeline.
After that the remaining (n - 1) results will come out at each clock cycle.
It therefore takes (k + n - 1) clock cycles to complete the task.