25-08-2017, 09:32 PM
Low Power UART Design for Serial Data Communication
[attachment=48881]
INTRODUCTION
With the proliferation of portable electronic devices, power efficient
data transmission has become increasingly important. For serial data transfer,
universal asynchronous receiver / transmitter (UART) circuits are often
implemented because of their inherent design simplicity and application
specific versatility. Components such as laptop keyboards, palm pilot
organizers and modems are few examples of devices that employ UART
circuits. In this work, design and analysis of a robust UART architecture has
been carried out to minimize power consumption during both idle and
continuous modes of operation.
UART, an introduction
An UART (universal asynchronous receiver / transmitter) is
responsible for performing the main task in serial communications with
computers. The device changes incoming parallel information to serial data
which can be sent on a communication line. A second UART can be used to
receive the information. The UART performs all the tasks, timing, parity
checking, etc. needed for the communication. The only extra devices attached
are line driver chips capable of transforming the TTL level signals to line
voltages and vice versa.
To use the device in different environments, registers are accessible
to set or review the communication parameters. Setable parameters are for
example the communication speed, the type of parity check, and the way
incoming information is signaled to the running software.
UART types
Serial communication on PC compatibles started with the 8250
UART in the XT. In the years after, new family members were introduced like
the 8250A and 8250B revisions and the 16450. The last one was first
implemented in the AT. The higher bus speed in this computer could not be
reached by the 8250 series. The differences between these first UART series
were rather minor. The most important property changed with each new release
was the maximum allowed speed at the processor bus side.
The 16450 was capable of handling a communication speed of 38.4
kbs without problems. The demand for higher speeds led to the development of
newer series which would be able to release the main processor from some of
its tasks. The main problem with the original series was the need to perform a
software action for each single byte to transmit or receive. To overcome this
problem, the 16550 was released which contained two on-board FIFO buffers,
each capable of storing 16 bytes. One buffer for incoming, and one buffer for
outgoing bytes.
UART DESIGN AND PROTOCOL
Our basic UART design consists of four main components: two
counters, a shifter and a finite state machine which is shown in figure 1. The
system is initialized in the start state with Po through P9 (10 bit group) of the
shifter preset to values of ‘1’. The first two components CNT12 and CNT16,
divide the clock frequency down to the desired data transmission baud rate.
RESULTS AND DISCUSSIONS
Voltage – Scaling
Design optimization was carried out with the primary goal of
reducing the UART power consumption during both continuous and idle
modes of operation. The first approach used to minimize power consumption
was to scale the circuit operating voltage (Vdd). The power consumption of
CMOS circuits can be approximated by equation 1 where α is the activity
factor, fclk is the operating frequency, CL is the load capacitance and Vdd is the
supply voltage.
Complete power shutdown
Alternatively, the disabled Vdd signal can be sent to a 1volt DC-DC
converter. (Figure 8a) to implement a complete power shut down. The circuit
in figure 8a is simply a chain of inverters where the last inverter consists of
large width and high Vt PMOS and NMOS devices that acts as a switch. The
first two inverters are buffers to drive the large width devices. Using this
technique during the idle mode the leakage power for the UART is effectively 0. each wake up event takes approximately 100nseconds (figure 8b) along with
power consumption of 0.12mWatt.
The power shutdown technique shows approximately 91% power
reduction (this also takes into account the power consumption of the DC-DC
converter.) in idle mode power. If this technique is applied the converter
virtually eliminates all the leakage power of the UART in the idle mode.
However, since all nodes are completely discharged after a byte is
acknowledged the continuous mode power consumption is significantly
increased due to DC-DC converter having to recharge all nodes to initialize the
system.
[attachment=48881]
INTRODUCTION
With the proliferation of portable electronic devices, power efficient
data transmission has become increasingly important. For serial data transfer,
universal asynchronous receiver / transmitter (UART) circuits are often
implemented because of their inherent design simplicity and application
specific versatility. Components such as laptop keyboards, palm pilot
organizers and modems are few examples of devices that employ UART
circuits. In this work, design and analysis of a robust UART architecture has
been carried out to minimize power consumption during both idle and
continuous modes of operation.
UART, an introduction
An UART (universal asynchronous receiver / transmitter) is
responsible for performing the main task in serial communications with
computers. The device changes incoming parallel information to serial data
which can be sent on a communication line. A second UART can be used to
receive the information. The UART performs all the tasks, timing, parity
checking, etc. needed for the communication. The only extra devices attached
are line driver chips capable of transforming the TTL level signals to line
voltages and vice versa.
To use the device in different environments, registers are accessible
to set or review the communication parameters. Setable parameters are for
example the communication speed, the type of parity check, and the way
incoming information is signaled to the running software.
UART types
Serial communication on PC compatibles started with the 8250
UART in the XT. In the years after, new family members were introduced like
the 8250A and 8250B revisions and the 16450. The last one was first
implemented in the AT. The higher bus speed in this computer could not be
reached by the 8250 series. The differences between these first UART series
were rather minor. The most important property changed with each new release
was the maximum allowed speed at the processor bus side.
The 16450 was capable of handling a communication speed of 38.4
kbs without problems. The demand for higher speeds led to the development of
newer series which would be able to release the main processor from some of
its tasks. The main problem with the original series was the need to perform a
software action for each single byte to transmit or receive. To overcome this
problem, the 16550 was released which contained two on-board FIFO buffers,
each capable of storing 16 bytes. One buffer for incoming, and one buffer for
outgoing bytes.
UART DESIGN AND PROTOCOL
Our basic UART design consists of four main components: two
counters, a shifter and a finite state machine which is shown in figure 1. The
system is initialized in the start state with Po through P9 (10 bit group) of the
shifter preset to values of ‘1’. The first two components CNT12 and CNT16,
divide the clock frequency down to the desired data transmission baud rate.
RESULTS AND DISCUSSIONS
Voltage – Scaling
Design optimization was carried out with the primary goal of
reducing the UART power consumption during both continuous and idle
modes of operation. The first approach used to minimize power consumption
was to scale the circuit operating voltage (Vdd). The power consumption of
CMOS circuits can be approximated by equation 1 where α is the activity
factor, fclk is the operating frequency, CL is the load capacitance and Vdd is the
supply voltage.
Complete power shutdown
Alternatively, the disabled Vdd signal can be sent to a 1volt DC-DC
converter. (Figure 8a) to implement a complete power shut down. The circuit
in figure 8a is simply a chain of inverters where the last inverter consists of
large width and high Vt PMOS and NMOS devices that acts as a switch. The
first two inverters are buffers to drive the large width devices. Using this
technique during the idle mode the leakage power for the UART is effectively 0. each wake up event takes approximately 100nseconds (figure 8b) along with
power consumption of 0.12mWatt.
The power shutdown technique shows approximately 91% power
reduction (this also takes into account the power consumption of the DC-DC
converter.) in idle mode power. If this technique is applied the converter
virtually eliminates all the leakage power of the UART in the idle mode.
However, since all nodes are completely discharged after a byte is
acknowledged the continuous mode power consumption is significantly
increased due to DC-DC converter having to recharge all nodes to initialize the
system.