31-01-2013, 04:34 PM
80C196
[attachment=49126]
The 8xC196EA is the first member of a new family of microcontrollers.
With features that are useful in automotive applications, such as power train control.
Two Mbytes of linear address space provide more space for high-level language compilation.
A demultiplexed address/data bus and three chip-select signals make it easier to design low-cost memory solutions.
The external bus can dynamically switch between multiplexed and demultiplexed operation.
Features
40 MHz operation
Optional clock doubler
2 Mbytes of linear address space
1 Kbyte of register RAM
3 Kbytes of code RAM
8 Kbytes of ROM
Register-to-register architecture
Stack overflow/underflow monitor with user-defined upper and lower stack pointer boundary limits
2 peripheral interrupt handlers (PIH) provide direct hardware handling of up to 16 peripheral interrupts
Peripheral transaction server (PTS) with high-speed, micro-coded interrupt service routines
Memory controller
All of the program memory and external data memory are transferred to the CPU through the memory controller. The memory controller consists of a slave program counter, an instruction queue and a bus controller.
The slave program counter keeps track of the instructions fetched from the program memory. Instructions fetched by the memory controller are stored in the queue. The slave program counter may be up to four bytes ahead of the main program counter (which is located in the RALU), because it is pre-fetching the instructions.
The bus controller accesses program memory (on-chip EPROM) and external data memory and arbitrates between instruction fetches and data reads and writes. The bus controller supports both 8-bit and 16-bit external bus modes. Memory access requests to the bus controller can come from either the RALU or the queue, with priority given to the queue accesses.
Memory space
Addressable space
The addressable memory space of the 80c196 consists of 64k bytes. However, not all these addresses are available to the user. Addresses 0000H through 00FFH and 1FFEH through 207FH are reserved for special purposes. All other locations can be used for either program or data storage, or for memory-mapped I/O.
Special Function Registers (SFRs)
Locations 00H through O17H are the I/O control registers or SFRs. All of the peripheral devices of the 80c196 except ports 3 and 4 are controlled through these registers. SFR functions are controlled through 3 windows. Switching between the windows is done using the WSR - Window Select Register located at address 014H. SFR windows other than WSR = 0 are out of the scope of this course.
Some of the Special Function Registers have different meanings if read from or written to.
Interrupts
Twenty-eight (28) sources of interrupts are available on the 80C196KB. These sources are gathered into 15 vectors plus special vectors for NMI, the TRAP instruction, and Unimplemented Opcodes.
Three special interrupts are available on the 80C196KB: NMI, TRAP and Unimplemented opcode. The external NMI pin generates an non-maskable interrupt for implementation of critical interrupt routines.
The TRAP instruction is useful in the development of custom software debuggers or generation of software interrupts.
Five registers control the operation of the interrupt system: INTÐPEND, INTÐPEND1, INTÐMASK and INTÐMASK1 and the PSW which contains a global disable bit.
[attachment=49126]
The 8xC196EA is the first member of a new family of microcontrollers.
With features that are useful in automotive applications, such as power train control.
Two Mbytes of linear address space provide more space for high-level language compilation.
A demultiplexed address/data bus and three chip-select signals make it easier to design low-cost memory solutions.
The external bus can dynamically switch between multiplexed and demultiplexed operation.
Features
40 MHz operation
Optional clock doubler
2 Mbytes of linear address space
1 Kbyte of register RAM
3 Kbytes of code RAM
8 Kbytes of ROM
Register-to-register architecture
Stack overflow/underflow monitor with user-defined upper and lower stack pointer boundary limits
2 peripheral interrupt handlers (PIH) provide direct hardware handling of up to 16 peripheral interrupts
Peripheral transaction server (PTS) with high-speed, micro-coded interrupt service routines
Memory controller
All of the program memory and external data memory are transferred to the CPU through the memory controller. The memory controller consists of a slave program counter, an instruction queue and a bus controller.
The slave program counter keeps track of the instructions fetched from the program memory. Instructions fetched by the memory controller are stored in the queue. The slave program counter may be up to four bytes ahead of the main program counter (which is located in the RALU), because it is pre-fetching the instructions.
The bus controller accesses program memory (on-chip EPROM) and external data memory and arbitrates between instruction fetches and data reads and writes. The bus controller supports both 8-bit and 16-bit external bus modes. Memory access requests to the bus controller can come from either the RALU or the queue, with priority given to the queue accesses.
Memory space
Addressable space
The addressable memory space of the 80c196 consists of 64k bytes. However, not all these addresses are available to the user. Addresses 0000H through 00FFH and 1FFEH through 207FH are reserved for special purposes. All other locations can be used for either program or data storage, or for memory-mapped I/O.
Special Function Registers (SFRs)
Locations 00H through O17H are the I/O control registers or SFRs. All of the peripheral devices of the 80c196 except ports 3 and 4 are controlled through these registers. SFR functions are controlled through 3 windows. Switching between the windows is done using the WSR - Window Select Register located at address 014H. SFR windows other than WSR = 0 are out of the scope of this course.
Some of the Special Function Registers have different meanings if read from or written to.
Interrupts
Twenty-eight (28) sources of interrupts are available on the 80C196KB. These sources are gathered into 15 vectors plus special vectors for NMI, the TRAP instruction, and Unimplemented Opcodes.
Three special interrupts are available on the 80C196KB: NMI, TRAP and Unimplemented opcode. The external NMI pin generates an non-maskable interrupt for implementation of critical interrupt routines.
The TRAP instruction is useful in the development of custom software debuggers or generation of software interrupts.
Five registers control the operation of the interrupt system: INTÐPEND, INTÐPEND1, INTÐMASK and INTÐMASK1 and the PSW which contains a global disable bit.