04-02-2013, 03:24 PM
FINFET
[attachment=49568]
INTRODUCTION
Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.
PARTIALLY DEPLETED [PD] SOI
The PD floating-body MOSFET was the first SOI transistor generically adopted for high-performance applications, primarily due to device and processing similarities to bulk CMOS device.
The PD SOI device is largely identical to the bulk device, except for the addition of a buried oxide (“BOX”) layer. The active Si film thickness is larger than the channel depletion width, thus leaving a quasi-neutral “floating” body region underneath the channel. The V T of the device is completely decoupled from the Si film thickness, and the doping profiles can be tailored for any desired VT .
Parasitic Bipolar Effect
In PDSOI an n-p-n transistor is formed with source and drain as emitter & collector respectively and body as the base. The topology typically involves an “off” transistor with the source and drain voltage set up in the “high” state (hence body voltage at“high”) When the source is subsequently pulled down, large overdrive is developed across the body-source junction, causing bipolar current to flow through the lateral parasitic bipolar transistor.This may result in circuit failure.
Hysteretic VT Variation
The hysteretic VT variation due to long time constants of various
body charging/discharging mechanisms.
A commonly used gauge for hysteretic VT variation (or “history effect” as it is known in the SOI community) is the disparity in the body voltages and delays between the so-called “first switch” and “second switch” . The “first switch” refers to the case where a circuit (e.g., inverter) starts in an initial quiescent state with input “low” and then undergoes an input-rising transition. In this case, the initial dc equilibrium body potential of the switching nMOSFET is determined primarily by the balance of the back-to-back drain-to-body and body-to-source diodes. The “second switch” refers to the case where the circuit is initially in a quiescent state with input “high.” The input first falls and then rises (hence, the name “second switch”). For this case, the preswitch body voltage is determined by capacitive coupling between the drain and the body.
Self heating
The heat transfer is dominated by phonon transport in semiconductors and by electron transport in metals. The thermal conductivity of the buried oxide (1.4 W/m-.C) is about two orders of magnitude lower than that of Si (120 W/m-.C), giving rise to local self-heating in SOI devices. This is particularly a concern for devices that are “on” most or all the time (e.g., biasing elements, current source, current mirror, bleeder, etc.) and for circuits with high duty cycle and slow slew rate (such as clock distribution, I/O driver).
Scaling of the Si film degrades the thermal conductivity and increases the thermal resistance. In scaled SOI devices, both the channel length and Si film thickness are much smaller than the phonon mean free path for Si (~300 nm at room temperature), and the thermal conductivity is severely degraded due to phonon boundary scattering.
The thermal resistance increase is particularly significant for thinner Si film with thick buried oxide. As the Si film thickness is scaled further to approach the Phonon wavelength (~ tens of nm), the phonon confinement effect becomes significant. This is the mechanical/thermal analogy of the quantum confinement effect in electronic devices with an ultra-thin Si film. The boundary conditions change from the usual periodic boundary conditions for bulk materials to essentially zero displacements on the boundaries in SOI.
Soft Error Rate
The α-generated charges in SOI devices are substantially less than in bulk devices due to the presence of the buried oxide, and appreciable charge generation can only occur when an α-particle hits the channel region. While scaling of the device reduces the charge generation volume, the Qcrit also decreases due to a lower capacitance at the cell’s storage node and scaled VDD.
In a PD SOI device, the total charges accumulated at the cell storage node can be significantly higher than the α-generated charges due to the parasitic bipolar effect. For properly scaled PD SOI devices, the parasitic bipolar gain is reduced, and the resulting overall single-event-upset-induced failure rate is less than that of bulk silicon. Furthermore, scaling/thinning of the Si film reduces the charge generation volume and the base-emitter (body-source) junction area of the parasitic bipolar transistor, thus improving SER as well.
Strained-Si channel And High-k Gate
Strained-Si surface channel CMOS has recently emerged as an effective means of extending scaling for future high-performance applications due to higher mobility and improved Ion. The lattice mismatch between the Si channel and the underlying relaxed SiGe layer results in biaxial tensile strain, which reduces the intervalley scattering by increasing sub-band splitting and enhances carrier transport by reducing conductivity effective mass.
Combining strained si-channel and SOI complements the improved Ion of strained Si channel device with the benefit of SOI. However, there are numerous design implications. The narrower bandgap of the SiGe layer causes a heterostructural band offset, which reduces VT and increases Ioff. The mobility enhancement for nMOS and pMOS may be quite different due to device design and process integration constraints, which may upset the established β(p/n strength) ratio of existing designs. The tensile strain is “biaxial”, so mobility enhancements (therefore Ion improvement) are the same along X- and Y-axis. However, in some high-density design (eg: SRAM cell), “bent gates” at a 45° angle are sometimes used, which would result in disparity in mobility enhancement and Ion improvement. The SiGe layer with 20% Ge has a 70% higher dielectric constant and a 10% lower built-in potential due the narrower band gap, resulting in higher junction capacitance. Furthermore, higher body doping density could be needed to compensate for the VT reduction which further increases the junction capacitance. The thermal conductivity of the SiGe layer is about 15X lower than that for Si thus aggravating the self-heating effect
DOUBLE GATE FET
Double-gate CMOS (DGCMOS) offers distinct advantages for scaling to very short gate lengths. Fabrication of FinFET-DGCMOS is very close to that of conventional CMOS process, with only minor disruptions, offering the potential for a rapid deployment to manufacturing. Planar product designs have been converted to FinFET-DGCMOS without disruption to the physical area, thereby demonstrating its compatibility with today’s planar CMOS design methodology and automation techniques.
Overcoming Obstacles By Doubling Up
CMOS technology scaling has traversed many anticipated barriers over the past 20 years to rapidly progress from 2 µm to 90nm rules. Currently, two obstacles, namely subthreshold and gate-dielectric leakages, have become the dominant barrier for further CMOS scaling, even for highly leakage-tolerant applications such as microprocessors.
Double-gate (DG) FETs, in which a second gate is added opposite the traditional (first) gate, have better control over short-channel effects [SCEs]. SCE limits the minimum channel length at which an FET is electrically well behaved.
[attachment=49568]
INTRODUCTION
Since the fabrication of MOSFET, the minimum channel length has been shrinking continuously. The motivation behind this decrease has been an increasing interest in high speed devices and in very large scale integrated circuits. The sustained scaling of conventional bulk device requires innovations to circumvent the barriers of fundamental physics constraining the conventional MOSFET device structure. The limits most often cited are control of the density and location of dopants providing high I on /I off ratio and finite subthreshold slope and quantum-mechanical tunneling of carriers through thin gate from drain to source and from drain to body. The channel depletion width must scale with the channel length to contain the off-state leakage I off. This leads to high doping concentration, which degrade the carrier mobility and causes junction edge leakage due to tunneling. Furthermore, the dopant profile control, in terms of depth and steepness, becomes much more difficult. The gate oxide thickness tox must also scale with the channel length to maintain gate control, proper threshold voltage VT and performance. The thinning of the gate dielectric results in gate tunneling leakage, degrading the circuit performance, power and noise margin.
PARTIALLY DEPLETED [PD] SOI
The PD floating-body MOSFET was the first SOI transistor generically adopted for high-performance applications, primarily due to device and processing similarities to bulk CMOS device.
The PD SOI device is largely identical to the bulk device, except for the addition of a buried oxide (“BOX”) layer. The active Si film thickness is larger than the channel depletion width, thus leaving a quasi-neutral “floating” body region underneath the channel. The V T of the device is completely decoupled from the Si film thickness, and the doping profiles can be tailored for any desired VT .
Parasitic Bipolar Effect
In PDSOI an n-p-n transistor is formed with source and drain as emitter & collector respectively and body as the base. The topology typically involves an “off” transistor with the source and drain voltage set up in the “high” state (hence body voltage at“high”) When the source is subsequently pulled down, large overdrive is developed across the body-source junction, causing bipolar current to flow through the lateral parasitic bipolar transistor.This may result in circuit failure.
Hysteretic VT Variation
The hysteretic VT variation due to long time constants of various
body charging/discharging mechanisms.
A commonly used gauge for hysteretic VT variation (or “history effect” as it is known in the SOI community) is the disparity in the body voltages and delays between the so-called “first switch” and “second switch” . The “first switch” refers to the case where a circuit (e.g., inverter) starts in an initial quiescent state with input “low” and then undergoes an input-rising transition. In this case, the initial dc equilibrium body potential of the switching nMOSFET is determined primarily by the balance of the back-to-back drain-to-body and body-to-source diodes. The “second switch” refers to the case where the circuit is initially in a quiescent state with input “high.” The input first falls and then rises (hence, the name “second switch”). For this case, the preswitch body voltage is determined by capacitive coupling between the drain and the body.
Self heating
The heat transfer is dominated by phonon transport in semiconductors and by electron transport in metals. The thermal conductivity of the buried oxide (1.4 W/m-.C) is about two orders of magnitude lower than that of Si (120 W/m-.C), giving rise to local self-heating in SOI devices. This is particularly a concern for devices that are “on” most or all the time (e.g., biasing elements, current source, current mirror, bleeder, etc.) and for circuits with high duty cycle and slow slew rate (such as clock distribution, I/O driver).
Scaling of the Si film degrades the thermal conductivity and increases the thermal resistance. In scaled SOI devices, both the channel length and Si film thickness are much smaller than the phonon mean free path for Si (~300 nm at room temperature), and the thermal conductivity is severely degraded due to phonon boundary scattering.
The thermal resistance increase is particularly significant for thinner Si film with thick buried oxide. As the Si film thickness is scaled further to approach the Phonon wavelength (~ tens of nm), the phonon confinement effect becomes significant. This is the mechanical/thermal analogy of the quantum confinement effect in electronic devices with an ultra-thin Si film. The boundary conditions change from the usual periodic boundary conditions for bulk materials to essentially zero displacements on the boundaries in SOI.
Soft Error Rate
The α-generated charges in SOI devices are substantially less than in bulk devices due to the presence of the buried oxide, and appreciable charge generation can only occur when an α-particle hits the channel region. While scaling of the device reduces the charge generation volume, the Qcrit also decreases due to a lower capacitance at the cell’s storage node and scaled VDD.
In a PD SOI device, the total charges accumulated at the cell storage node can be significantly higher than the α-generated charges due to the parasitic bipolar effect. For properly scaled PD SOI devices, the parasitic bipolar gain is reduced, and the resulting overall single-event-upset-induced failure rate is less than that of bulk silicon. Furthermore, scaling/thinning of the Si film reduces the charge generation volume and the base-emitter (body-source) junction area of the parasitic bipolar transistor, thus improving SER as well.
Strained-Si channel And High-k Gate
Strained-Si surface channel CMOS has recently emerged as an effective means of extending scaling for future high-performance applications due to higher mobility and improved Ion. The lattice mismatch between the Si channel and the underlying relaxed SiGe layer results in biaxial tensile strain, which reduces the intervalley scattering by increasing sub-band splitting and enhances carrier transport by reducing conductivity effective mass.
Combining strained si-channel and SOI complements the improved Ion of strained Si channel device with the benefit of SOI. However, there are numerous design implications. The narrower bandgap of the SiGe layer causes a heterostructural band offset, which reduces VT and increases Ioff. The mobility enhancement for nMOS and pMOS may be quite different due to device design and process integration constraints, which may upset the established β(p/n strength) ratio of existing designs. The tensile strain is “biaxial”, so mobility enhancements (therefore Ion improvement) are the same along X- and Y-axis. However, in some high-density design (eg: SRAM cell), “bent gates” at a 45° angle are sometimes used, which would result in disparity in mobility enhancement and Ion improvement. The SiGe layer with 20% Ge has a 70% higher dielectric constant and a 10% lower built-in potential due the narrower band gap, resulting in higher junction capacitance. Furthermore, higher body doping density could be needed to compensate for the VT reduction which further increases the junction capacitance. The thermal conductivity of the SiGe layer is about 15X lower than that for Si thus aggravating the self-heating effect
DOUBLE GATE FET
Double-gate CMOS (DGCMOS) offers distinct advantages for scaling to very short gate lengths. Fabrication of FinFET-DGCMOS is very close to that of conventional CMOS process, with only minor disruptions, offering the potential for a rapid deployment to manufacturing. Planar product designs have been converted to FinFET-DGCMOS without disruption to the physical area, thereby demonstrating its compatibility with today’s planar CMOS design methodology and automation techniques.
Overcoming Obstacles By Doubling Up
CMOS technology scaling has traversed many anticipated barriers over the past 20 years to rapidly progress from 2 µm to 90nm rules. Currently, two obstacles, namely subthreshold and gate-dielectric leakages, have become the dominant barrier for further CMOS scaling, even for highly leakage-tolerant applications such as microprocessors.
Double-gate (DG) FETs, in which a second gate is added opposite the traditional (first) gate, have better control over short-channel effects [SCEs]. SCE limits the minimum channel length at which an FET is electrically well behaved.