06-02-2013, 02:51 PM
8 Kbit Serial I2C Bus EEPROM with User-Defined Block Write Protection
[attachment=49840]
DESCRIPTION
This specification covers a range of 8 Kbits I2C bus
EEPROM products, the ST24/25C08 and the
ST24/25W08. In the text, products are referred to
as ST24/25x08, where "x" is: "C" for Standard
version and "W" for Hardware Write Control version.
The ST24/25x08 are 8 Kbit electrically erasable
programmable memories (EEPROM), organized
as 4 blocks of 256 x8 bits. They are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endurance
of one million erase/write cycles with a data
retention of 40 years.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
The memories are compatible with the I2C standard,
two wire serial interface which uses a bi-directional
data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2C bus definition.
This is used together with 1 chip enable input
(E) so that up to 2 x 8K devices may be attached
to the I2C bus and selected individually. The memories
behave as a slave device in the I2C protocol
with all memory operations synchronized by the
serial clock. Read and write operations are initiated
by a START condition generated by the bus master.
The START condition is followed by a stream of 7
bits (identification code 1010), plus one read/write
bit and terminated by an acknowledge bit.
DEVICE OPERATION
I2C Bus Background
The ST24/25x08 support the I2C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for synchronisation.
The ST24/25x08 are always slave
devices in all communications.
Write Operations
The Multibyte Write mode (only available on the
ST24/25C08 versions) is selected when the MODE
pin is at VIH and the Page Write mode when MODE
pin is at VIL. The MODE pin may be driven dynamically
with CMOS input levels.
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 8 bits provides access
to one block of 256 bytes of the memory.
Read Operations
Read operations are independent of the state of the
MODE pin. On delivery, the memory content is set
at all "1’s" (or FFh).
Current Address Read. The memory has an internal
byte address counter. Each time a byte is read,
this counter is incremented. For the Current Address
Read mode, following a START condition,
the master sends a memory address with the RW
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master does NOT acknowledge the byte output,
but terminates the transfer with a STOP condition.
[attachment=49840]
DESCRIPTION
This specification covers a range of 8 Kbits I2C bus
EEPROM products, the ST24/25C08 and the
ST24/25W08. In the text, products are referred to
as ST24/25x08, where "x" is: "C" for Standard
version and "W" for Hardware Write Control version.
The ST24/25x08 are 8 Kbit electrically erasable
programmable memories (EEPROM), organized
as 4 blocks of 256 x8 bits. They are manufactured
in STMicroelectronics’s Hi-Endurance Advanced
CMOS technology which guarantees an endurance
of one million erase/write cycles with a data
retention of 40 years.
Both Plastic Dual-in-Line and Plastic Small Outline
packages are available.
The memories are compatible with the I2C standard,
two wire serial interface which uses a bi-directional
data bus and serial clock. The memories
carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2C bus definition.
This is used together with 1 chip enable input
(E) so that up to 2 x 8K devices may be attached
to the I2C bus and selected individually. The memories
behave as a slave device in the I2C protocol
with all memory operations synchronized by the
serial clock. Read and write operations are initiated
by a START condition generated by the bus master.
The START condition is followed by a stream of 7
bits (identification code 1010), plus one read/write
bit and terminated by an acknowledge bit.
DEVICE OPERATION
I2C Bus Background
The ST24/25x08 support the I2C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for synchronisation.
The ST24/25x08 are always slave
devices in all communications.
Write Operations
The Multibyte Write mode (only available on the
ST24/25C08 versions) is selected when the MODE
pin is at VIH and the Page Write mode when MODE
pin is at VIL. The MODE pin may be driven dynamically
with CMOS input levels.
Following a START condition the master sends a
device select code with the RW bit reset to ’0’. The
memory acknowledges this and waits for a byte
address. The byte address of 8 bits provides access
to one block of 256 bytes of the memory.
Read Operations
Read operations are independent of the state of the
MODE pin. On delivery, the memory content is set
at all "1’s" (or FFh).
Current Address Read. The memory has an internal
byte address counter. Each time a byte is read,
this counter is incremented. For the Current Address
Read mode, following a START condition,
the master sends a memory address with the RW
bit set to ’1’. The memory acknowledges this and
outputs the byte addressed by the internal byte
address counter. This counter is then incremented.
The master does NOT acknowledge the byte output,
but terminates the transfer with a STOP condition.