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VLSI System Design Lab


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RTL Code

RTL Code –Timer 8254
Specifications
Data In Rate - 166.66 Mbps
Data Out Rate – 333.33 Mbps
Clock – 120ns
RTL Code was checked and errors were corrected.


Setting Timing Constraints


Defining the clock
Clock cycle time – 3 ns
Duty Cycle – 50%
Clock Network Latency – 100 ps (port to Register)
Clock Skew – Rise & Fall Setup uncertainity – 75 ps & 50 ps
Clock Skew – Rise & Fall Hold uncertainity – 75 ps & 50 ps


Setting Timing Constraints


Defining External Delays
Defining Input Delays-represents the arrival time of external paths at an input port relative to a clock edge
All input signals are set early by 50 ps with respect to clock edge
Defining Output Delays - represents the delay of an external timing path from an output port to a register input of the external block
All output signals are set late by 50 ps with respect to clock edge



Setting Timing Constraints


Setting path delays
When synthesized, 4 paths were found with maximum propagation delay in long run.
So, path delays were set for these 4 paths & reduced further for minimum path delays.
Final path delay obtained < 1000 ps