14-02-2013, 04:37 PM
M TECH ELECTRONICS WITH SPECIALIZATION IN VLSI AND EMBEDDED SYSTEMS
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ELV3101/ SP 102 ADVANCED DIGITAL SYSTEM DESIGN
Unit 1
MSI and LSI circuits and their applications: Arithmetic circuits, comparators, Multiplexers, Code Converters, XOR & AOI Gates, Design of sequential systems with small number of standard modules, State register Counters and RAM with combinational networks Multimodule implementation of sequential systems - Multimodule registers - and counters.
Unit 2
Sequential Circuit Design: Clocked Synchronous State Machine Analysis, Mealy and Moore machines, Finite State Machine design procedure – derive state diagrams and state tables, state reduction methods, and state assignments. Incompletely specified state machines. Implementing the states of FSM.
Unit 3
Asynchronous sequential circuits: Analysis, Derivation of excitation table, Flow table reduction, state assignment, transition table , design of asynchronous Sequential circuits, Race conditions and cycles, Static and dynamic hazards, Methods for avoiding races and hazards, essential hazards
Designing with SM charts – State machine charts, Derivation of SM charts, and Realization of SM charts.
Unit 4
Designing with Programmable Logic Devices: Read – Only Memories, Programmable Array Logic PALs, Programmable Logic Arrays PLAs – PLA minimization and PLA folding, Other Sequential PLDs, Design of combinational and sequential circuits using PLD’s. Complex Programmable Logic Devices and Filed Programmable Gate Arrays - Altera Series FPGAs and Xilinx Series FPGAs
Unit 5
Timing issues in Digital system design: timing classification- synchronous timing basics – skew and jitter- latch based clocking- self timed circuit design - self timed logic, completion signal generation, self timed signaling–synchronizers and arbiters.
ELV 3102 VLSI TECHNOLOGY & DESIGN
Unit 1
Review of Microelectronics and Introduction to MOS Technologies: Technology trends . MOS Transistor Theory: n MOS / p MOS transistor, threshold voltage equation, body effect, MOS device design equation, sub threshold region, Channel length modulation. Mobility variation, tunneling, punch through, hot electron effect, Modelling of MOS transistors using SPICE.
Unit 2
Basic IC Processing Steps: Crystal growth and wafer preparation, epitaxy,Oxidation, Lithography, Etching techniques , film deposition, Diffusion, Ion implantation, metallisation, VLSI Process Integration NMOS, CMOS and BICMOS
Unit 3
Basics of Digital CMOS Design: The MOS Inverter: principle, Depletion and enhancement load inverters, the basic CMOS inverter, transfer characteristics, logic threshold, Noise margins, and Dynamic behavior, Propagation Delay, Power Consumption. Latch-up in CMOS circuits. Ratioed logic, Pass Transistor logic, Arithmetic circuits in CMOS VLSI; Adders- multipliers- shifters.
Unit 4
Sequential MOS Logic Design: Static latches; Flip flops & Registers, Dynamic Latches & Registers, CMOS Schmitt trigger, Monostable sequential Circuits, Astable Circuits. Memory Design: ROM & RAM cells design, SRAM and DRAM, Domino and NORA logic.
Unit 5
Circuit design Process : Circuit elements- resistor , capacitor, interconnects, sheet resistance , standard unit capacitance and unit delay concepts , inverter delays , driving capacitive loads, propagation delays, MOS layers, Stick diagrams and mask layout encoding, Design rules and layout, Lambda Based Design rules, micron based design rules, scaling of MOS circuits.
[attachment=50955]
ELV3101/ SP 102 ADVANCED DIGITAL SYSTEM DESIGN
Unit 1
MSI and LSI circuits and their applications: Arithmetic circuits, comparators, Multiplexers, Code Converters, XOR & AOI Gates, Design of sequential systems with small number of standard modules, State register Counters and RAM with combinational networks Multimodule implementation of sequential systems - Multimodule registers - and counters.
Unit 2
Sequential Circuit Design: Clocked Synchronous State Machine Analysis, Mealy and Moore machines, Finite State Machine design procedure – derive state diagrams and state tables, state reduction methods, and state assignments. Incompletely specified state machines. Implementing the states of FSM.
Unit 3
Asynchronous sequential circuits: Analysis, Derivation of excitation table, Flow table reduction, state assignment, transition table , design of asynchronous Sequential circuits, Race conditions and cycles, Static and dynamic hazards, Methods for avoiding races and hazards, essential hazards
Designing with SM charts – State machine charts, Derivation of SM charts, and Realization of SM charts.
Unit 4
Designing with Programmable Logic Devices: Read – Only Memories, Programmable Array Logic PALs, Programmable Logic Arrays PLAs – PLA minimization and PLA folding, Other Sequential PLDs, Design of combinational and sequential circuits using PLD’s. Complex Programmable Logic Devices and Filed Programmable Gate Arrays - Altera Series FPGAs and Xilinx Series FPGAs
Unit 5
Timing issues in Digital system design: timing classification- synchronous timing basics – skew and jitter- latch based clocking- self timed circuit design - self timed logic, completion signal generation, self timed signaling–synchronizers and arbiters.
ELV 3102 VLSI TECHNOLOGY & DESIGN
Unit 1
Review of Microelectronics and Introduction to MOS Technologies: Technology trends . MOS Transistor Theory: n MOS / p MOS transistor, threshold voltage equation, body effect, MOS device design equation, sub threshold region, Channel length modulation. Mobility variation, tunneling, punch through, hot electron effect, Modelling of MOS transistors using SPICE.
Unit 2
Basic IC Processing Steps: Crystal growth and wafer preparation, epitaxy,Oxidation, Lithography, Etching techniques , film deposition, Diffusion, Ion implantation, metallisation, VLSI Process Integration NMOS, CMOS and BICMOS
Unit 3
Basics of Digital CMOS Design: The MOS Inverter: principle, Depletion and enhancement load inverters, the basic CMOS inverter, transfer characteristics, logic threshold, Noise margins, and Dynamic behavior, Propagation Delay, Power Consumption. Latch-up in CMOS circuits. Ratioed logic, Pass Transistor logic, Arithmetic circuits in CMOS VLSI; Adders- multipliers- shifters.
Unit 4
Sequential MOS Logic Design: Static latches; Flip flops & Registers, Dynamic Latches & Registers, CMOS Schmitt trigger, Monostable sequential Circuits, Astable Circuits. Memory Design: ROM & RAM cells design, SRAM and DRAM, Domino and NORA logic.
Unit 5
Circuit design Process : Circuit elements- resistor , capacitor, interconnects, sheet resistance , standard unit capacitance and unit delay concepts , inverter delays , driving capacitive loads, propagation delays, MOS layers, Stick diagrams and mask layout encoding, Design rules and layout, Lambda Based Design rules, micron based design rules, scaling of MOS circuits.