18-02-2013, 10:10 AM
Generating HDL Code Using MATLAB Commands
[attachment=51257]
Overview
This exercise provides a step-by-step introduction to the Simulink HDL Coder code and test bench generation
commands, their arguments, and the files created by the code generator. The exercise assumes that you have
familiarized yourself with the demo model (see The sfir_fixed Demo Model).
Initializing Model Parameters with hdlsetup
Before generating code, you must set some parameters of the model. Rather than doing this manually, use the
Simulink HDL Coder M-file utility, hdlsetup.m. The hdlsetup command uses the Simulink set_param
function to set up models for HDL code generation quickly and consistently.
Generating a VHDL Entity from a Subsystem
In this section, you will use the makehdl function to generate code for a VHDL entity from the symmetric_fir
subsystem of the demo model. makehdl also generates script files for third-party HDL simulation and synthesis
tools.
makehdl lets you specify numerous properties that control various features of the generated code. In this
example, you will use defaults for all makehdl properties.
Generating VHDL Test Bench Code
In this section, you use the Simulink HDL Coder test bench generation function, makehdltb, to generate a
VHDL test bench. The test bench is designed to drive and verify the operation of the symmetric_fir entity
that was generated in the previous section. A generated test bench includes
Stimulus data generated by signal sources connected to the entity under test.
Output data generated by the entity under test. During a test bench run, this data is compared to the
outputs of the VHDL model, for verification purposes.
Clock, reset, and clock enable inputs to drive the entity under test.
A component instantiation of the entity under test.
Code to drive the entity under test and compare its outputs to the expected data.
[attachment=51257]
Overview
This exercise provides a step-by-step introduction to the Simulink HDL Coder code and test bench generation
commands, their arguments, and the files created by the code generator. The exercise assumes that you have
familiarized yourself with the demo model (see The sfir_fixed Demo Model).
Initializing Model Parameters with hdlsetup
Before generating code, you must set some parameters of the model. Rather than doing this manually, use the
Simulink HDL Coder M-file utility, hdlsetup.m. The hdlsetup command uses the Simulink set_param
function to set up models for HDL code generation quickly and consistently.
Generating a VHDL Entity from a Subsystem
In this section, you will use the makehdl function to generate code for a VHDL entity from the symmetric_fir
subsystem of the demo model. makehdl also generates script files for third-party HDL simulation and synthesis
tools.
makehdl lets you specify numerous properties that control various features of the generated code. In this
example, you will use defaults for all makehdl properties.
Generating VHDL Test Bench Code
In this section, you use the Simulink HDL Coder test bench generation function, makehdltb, to generate a
VHDL test bench. The test bench is designed to drive and verify the operation of the symmetric_fir entity
that was generated in the previous section. A generated test bench includes
Stimulus data generated by signal sources connected to the entity under test.
Output data generated by the entity under test. During a test bench run, this data is compared to the
outputs of the VHDL model, for verification purposes.
Clock, reset, and clock enable inputs to drive the entity under test.
A component instantiation of the entity under test.
Code to drive the entity under test and compare its outputs to the expected data.