23-02-2013, 04:36 PM
Low power Uart design for serial data communication
[attachment=51684]
HISTORY OF UART
The first UART-like devices (with fixed-length pulses) were rotating mechanical switches (commutators).
The Western made Single-chip UART WD1402A around 1971.
Then Motorola introduced around 1975.
After it National Semiconductor introduced around 1980’s.
UART TYPES
Serial communication on PC compatibles started with the 8250.
New family members introduced 8250A and 8250B revisions and the 16450.
The 16450 was capable of handling a communication speed of 38.4kbs without problems.
16550 released which contained two on-board FIFO buffers each capable of storing 16 bytes.
UART DESIGN AND PROTOCOL
The first two components CNT12 and CNT16,
divide the clock frequency down to the desired data transmission baud rate.
The finite state machine (FSM) is initially in the start state where it waits for a falling edge of the serial in data to signal in the start of an incoming10-bit word.
CONCLUSION
low power configurations were examined to minimize the UART power consumption.
complete power shutdown allows zero leakage current for the UART in idle mode.
the idle mode power for the DC-DC converter circuit was seen to be larger than the UART idle power with MT – CMOS.
[attachment=51684]
HISTORY OF UART
The first UART-like devices (with fixed-length pulses) were rotating mechanical switches (commutators).
The Western made Single-chip UART WD1402A around 1971.
Then Motorola introduced around 1975.
After it National Semiconductor introduced around 1980’s.
UART TYPES
Serial communication on PC compatibles started with the 8250.
New family members introduced 8250A and 8250B revisions and the 16450.
The 16450 was capable of handling a communication speed of 38.4kbs without problems.
16550 released which contained two on-board FIFO buffers each capable of storing 16 bytes.
UART DESIGN AND PROTOCOL
The first two components CNT12 and CNT16,
divide the clock frequency down to the desired data transmission baud rate.
The finite state machine (FSM) is initially in the start state where it waits for a falling edge of the serial in data to signal in the start of an incoming10-bit word.
CONCLUSION
low power configurations were examined to minimize the UART power consumption.
complete power shutdown allows zero leakage current for the UART in idle mode.
the idle mode power for the DC-DC converter circuit was seen to be larger than the UART idle power with MT – CMOS.