25-02-2013, 11:30 AM
Cadence® NC-Verilog® Simulator Help
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Native Compiled Code
Native compiled code (NCC) is a software execution technique that provides a
high-performance solution to the simulation performance bottleneck. In an NCC simulator, a
parser produces an intermediate representation of the input source text. This intermediate
representation is then processed by a code generator that produces relocatable machine
code that runs directly on the host processor.
The Interleaved Native Compiled Code (INCA)
Architecture
The Interleaved Native Compiled Code Architecture (INCA) is an extension of the Native
Compiled Code (NCC) approach to software execution.
The NCC approach to simulation addresses the performance challenge of a single-simulation
strategy. However, many new factors are rapidly making single-language, event-driven,
HDL-based simulation ineffective. These include:
Increased design sizes that require a mixture of behavioral, rtl, and gate-level simulation
for verification
Intellectual property block usage and/or embedded block reuse that necessitate
multilanguage environments
Asynchronous, critical-path timing accuracy requirements that increase the emphasis on
mixed-signal simulation
Synchronous design simulation performance requirements that increase the emphasis
on cycle simulation
The Cadence Desktop Simulators
The Cadence Verilog Desktop, VHDL Desktop, and NC-Sim Desktop simulator products are
low-cost, lower-performance versions of the full-performance NC-Verilog, NC-VHDL, and
NC-Sim simulators. The Desktop products are available only on Windows NT and
Windows2000 platforms.
The features and functionality of the Desktop products are the same as the full-performance
simulators with the following differences:
Memory Requirements
As with any simulator, memory requirements for the NC-Verilog simulator are highly
dependent on the size of the design. In order to achieve the highest performance possible,
you must have enough memory to compile and elaborate the design efficiently, and, during
the actual simulation phase, you should have enough memory so that the design resides in
physical memory.
For RTL designs, a minimum of 64 Mb is required for both building and simulating the design.
For a gate-level design of about 150K gates, 128 Mb is recommended for optimal build time.
For simulation, 64 Mb should be sufficient
[attachment=51735]
Native Compiled Code
Native compiled code (NCC) is a software execution technique that provides a
high-performance solution to the simulation performance bottleneck. In an NCC simulator, a
parser produces an intermediate representation of the input source text. This intermediate
representation is then processed by a code generator that produces relocatable machine
code that runs directly on the host processor.
The Interleaved Native Compiled Code (INCA)
Architecture
The Interleaved Native Compiled Code Architecture (INCA) is an extension of the Native
Compiled Code (NCC) approach to software execution.
The NCC approach to simulation addresses the performance challenge of a single-simulation
strategy. However, many new factors are rapidly making single-language, event-driven,
HDL-based simulation ineffective. These include:
Increased design sizes that require a mixture of behavioral, rtl, and gate-level simulation
for verification
Intellectual property block usage and/or embedded block reuse that necessitate
multilanguage environments
Asynchronous, critical-path timing accuracy requirements that increase the emphasis on
mixed-signal simulation
Synchronous design simulation performance requirements that increase the emphasis
on cycle simulation
The Cadence Desktop Simulators
The Cadence Verilog Desktop, VHDL Desktop, and NC-Sim Desktop simulator products are
low-cost, lower-performance versions of the full-performance NC-Verilog, NC-VHDL, and
NC-Sim simulators. The Desktop products are available only on Windows NT and
Windows2000 platforms.
The features and functionality of the Desktop products are the same as the full-performance
simulators with the following differences:
Memory Requirements
As with any simulator, memory requirements for the NC-Verilog simulator are highly
dependent on the size of the design. In order to achieve the highest performance possible,
you must have enough memory to compile and elaborate the design efficiently, and, during
the actual simulation phase, you should have enough memory so that the design resides in
physical memory.
For RTL designs, a minimum of 64 Mb is required for both building and simulating the design.
For a gate-level design of about 150K gates, 128 Mb is recommended for optimal build time.
For simulation, 64 Mb should be sufficient