06-03-2013, 03:36 PM
The Itanium Processor
[attachment=52790]
ABSTRACT
The Itanium brand extends Intel’s reach into the highest level of computing enabling powerful servers and high- performance workstations to address the increasing demands that the internet economy places on e-business. The Itanium architecture is a unique combination of innovative features, such as explicit parallelism, predication, speculation and much more.
In addition to providing much more memory that today’s 32-bit designs, the 64-bit architecture changes the way the processor hardware interacts with code. The Itanium is geared toward increasingly power-hungry applications like e-commerce security, computer-aided design and scientific modeling.
Intel said the Itanium provides a 12-fold performance improvement over today’s 32-bit designs. Its “Explicitly Parallel Instruction Computing”(EPIC) technology enables it to handle parallel processing differently than previous architectures, most of which were designed 10 to 20 years ago. The technology reduces hardware complexity to better enable processor speed upgrades. Itanium processors contain “massive chip execution resources”, that allow “breakthrough capabilities in processing terabytes of data”.
INTRODUCTION
The Itanium processor family came about for several reasons, but the primary one was that the processor architecture advances of RISC were no longer growing at the rate seen in the 1980’s or the 1990’s.Yet,customers continued demand greater application performance. The Itanium processor family was developed as a response to address the future performance and growth needs of business, technical and scientific users with greater flexibility, better performance and a much greater ‘bang for the buck’ in the price performance arena. Itanium is the first processor to use EPIC(Explicit Parallel Instruction Computing) architecture. Its performance is to be better than the present day Reduced Instruction Set Computing and Complex Instruction Set Computing(RISC & CISC).
SEQUENTIAL SEMANTICS
A program is a sequence of instructions. It has an implied order of instruction execution. So there is a potential dependence from instruction to instruction. But high performance needs parallel execution which in turn needs independent instructions. So independent instructions must be rediscovered by the hardware.
LOW INSTRUCTION LEVEL PARALLELISM(ILP)
In present day programs branches are frequent. As a result code blocks are small. So parallelism is limited within the code blocks. Wider machines need more parallel instructions. So ILP across the branches need to be exploited. But when this is done some instructions can fault due to wrong prediction. In short branches are a barrier to code motion.
BRANCH UNPREDICTABILITY
Branch predictions are not perfect. When wrong it leads to performance penalty. It is more if the instructions which went wrong consist of memory operations (loads & stores) or floating point operations. Also if exception on speculative operations, we need to defer it. This results in more book keeping hardware.
MEMORY DEPENDENCIES
Usually load instructions are at the top of a chain of instructions. ILP requires moving these loads. Store instructions are also a barrier. Dynamic disambiguation has its limitations For it requires additional hardware and it adds to the code size if done in software.
MEMORY LATENCY
Though the speed of A.L.U, decoders and other execution units have increased with time, the advances in technologies related to memories is not in pace with it. So even if the decoding and further execution of the instruction is fast ,the memory fetch which is needed prior to it takes time and leads to reduced pace of program execution. The cache hierarchy which reduces the memory latency has its limitations. It is managed asynchronously by hardware and helps only if there is locality. Also it consumes precious silicon area.
RESOURCE CONSTRAINTS
Small register space creates false dependencies. Shared resources like conditional flags and conditional registers force dependencies on independent instructions. Floating point resources are limited and not flexible.
PROCEDURE CALL & LOOP PIPELINING OVERHEAD
As modular programming is increasingly used the programs tend to be call intensive. Register space is shared by caller and calle. Call/return requires register save/restore.
Though loops are common sources of good ILP Unrolling/Pipelining is needed to exploit this ILP. Prologue/Epilogue causes code expansion. So the applicability of these techniques is limited.
RSE(REGISTER STACK ENGINE)
GR stack reduces need for save/restore across call. Also Itanium has a procedure stack frame of programmable size(0 to 96 registers).This mechanism is implemented by renaming registers. RSE automatically saves\restores registers without software intervention. It provides the illusion of infinite physical registers. RSE may be designed to utilize unused memory bandwidth to perform register spill and fill operations in the background.
MASSIVE MEMORY RESOURCES
• 8 billion Gigabytes accessible
• Both 64 bit and 32 bit pointers supported
• Both Little Endian and Big Endian order supported
REGISTERS
• 128 64-bit general purpose registers, named GR0-GR127.GR0 always reads 0 when sourced as an operand.
• 128 82-bit floating point registers, named FR0-FR127.FR0 always reads +0.0 when sourced,FR1 always reads +1.0 when sourced. Format consists of 1-bit sign|17-bit exp|64-bit explicit one mantissa.
• 64 1-bit predicate registers, named PR0-PR63.PR0 always reads 1.
• 8 64-bit branch registers, named BR0-BR7.Used to hold indirect branching information.
8 64-bit kernel registers, named KR0-KR7.Used to communicate information from the kernel to an application.
[attachment=52790]
ABSTRACT
The Itanium brand extends Intel’s reach into the highest level of computing enabling powerful servers and high- performance workstations to address the increasing demands that the internet economy places on e-business. The Itanium architecture is a unique combination of innovative features, such as explicit parallelism, predication, speculation and much more.
In addition to providing much more memory that today’s 32-bit designs, the 64-bit architecture changes the way the processor hardware interacts with code. The Itanium is geared toward increasingly power-hungry applications like e-commerce security, computer-aided design and scientific modeling.
Intel said the Itanium provides a 12-fold performance improvement over today’s 32-bit designs. Its “Explicitly Parallel Instruction Computing”(EPIC) technology enables it to handle parallel processing differently than previous architectures, most of which were designed 10 to 20 years ago. The technology reduces hardware complexity to better enable processor speed upgrades. Itanium processors contain “massive chip execution resources”, that allow “breakthrough capabilities in processing terabytes of data”.
INTRODUCTION
The Itanium processor family came about for several reasons, but the primary one was that the processor architecture advances of RISC were no longer growing at the rate seen in the 1980’s or the 1990’s.Yet,customers continued demand greater application performance. The Itanium processor family was developed as a response to address the future performance and growth needs of business, technical and scientific users with greater flexibility, better performance and a much greater ‘bang for the buck’ in the price performance arena. Itanium is the first processor to use EPIC(Explicit Parallel Instruction Computing) architecture. Its performance is to be better than the present day Reduced Instruction Set Computing and Complex Instruction Set Computing(RISC & CISC).
SEQUENTIAL SEMANTICS
A program is a sequence of instructions. It has an implied order of instruction execution. So there is a potential dependence from instruction to instruction. But high performance needs parallel execution which in turn needs independent instructions. So independent instructions must be rediscovered by the hardware.
LOW INSTRUCTION LEVEL PARALLELISM(ILP)
In present day programs branches are frequent. As a result code blocks are small. So parallelism is limited within the code blocks. Wider machines need more parallel instructions. So ILP across the branches need to be exploited. But when this is done some instructions can fault due to wrong prediction. In short branches are a barrier to code motion.
BRANCH UNPREDICTABILITY
Branch predictions are not perfect. When wrong it leads to performance penalty. It is more if the instructions which went wrong consist of memory operations (loads & stores) or floating point operations. Also if exception on speculative operations, we need to defer it. This results in more book keeping hardware.
MEMORY DEPENDENCIES
Usually load instructions are at the top of a chain of instructions. ILP requires moving these loads. Store instructions are also a barrier. Dynamic disambiguation has its limitations For it requires additional hardware and it adds to the code size if done in software.
MEMORY LATENCY
Though the speed of A.L.U, decoders and other execution units have increased with time, the advances in technologies related to memories is not in pace with it. So even if the decoding and further execution of the instruction is fast ,the memory fetch which is needed prior to it takes time and leads to reduced pace of program execution. The cache hierarchy which reduces the memory latency has its limitations. It is managed asynchronously by hardware and helps only if there is locality. Also it consumes precious silicon area.
RESOURCE CONSTRAINTS
Small register space creates false dependencies. Shared resources like conditional flags and conditional registers force dependencies on independent instructions. Floating point resources are limited and not flexible.
PROCEDURE CALL & LOOP PIPELINING OVERHEAD
As modular programming is increasingly used the programs tend to be call intensive. Register space is shared by caller and calle. Call/return requires register save/restore.
Though loops are common sources of good ILP Unrolling/Pipelining is needed to exploit this ILP. Prologue/Epilogue causes code expansion. So the applicability of these techniques is limited.
RSE(REGISTER STACK ENGINE)
GR stack reduces need for save/restore across call. Also Itanium has a procedure stack frame of programmable size(0 to 96 registers).This mechanism is implemented by renaming registers. RSE automatically saves\restores registers without software intervention. It provides the illusion of infinite physical registers. RSE may be designed to utilize unused memory bandwidth to perform register spill and fill operations in the background.
MASSIVE MEMORY RESOURCES
• 8 billion Gigabytes accessible
• Both 64 bit and 32 bit pointers supported
• Both Little Endian and Big Endian order supported
REGISTERS
• 128 64-bit general purpose registers, named GR0-GR127.GR0 always reads 0 when sourced as an operand.
• 128 82-bit floating point registers, named FR0-FR127.FR0 always reads +0.0 when sourced,FR1 always reads +1.0 when sourced. Format consists of 1-bit sign|17-bit exp|64-bit explicit one mantissa.
• 64 1-bit predicate registers, named PR0-PR63.PR0 always reads 1.
• 8 64-bit branch registers, named BR0-BR7.Used to hold indirect branching information.
8 64-bit kernel registers, named KR0-KR7.Used to communicate information from the kernel to an application.