16-04-2013, 03:03 PM
Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes
[attachment=53082]
Abstract
In this work, we derive three novel composite field arithmetic
(CFA) Advanced Encryption Standard (AES) S-boxes of the field. The best construction is selected after a sequence of
algorithmic and architectural optimization processes. Furthermore, for
each composite field constructions, there exists eight possible isomorphic
mappings. Therefore, after the exploitation of a new common subexpression
elimination algorithm, the isomorphic mapping that results in the
minimal implementation area cost is chosen. High throughput hardware
implementations of our proposed CFA AES S-boxes are reported towards
the end of this paper. Through the exploitation of both algebraic normal
form and seven stages fine-grained pipelining, our best case achieves a
throughput 3.49 Gbps on a Cyclone II EP2C5T144C6 field-programmable
gate array.
INTRODUCTION
The Advanced Encryption Standard (AES) is an encryption standard
chosen by the National Institute of Standards and Technology (NIST) in
2001, which has its origin in the Rijndael block cipher. Several studies
in the area had identified the nonlinear SubBytes transformation as the
major bottleneck in achieving both small area and high speed VLSI
AES implementations [1].
This brief presents a methodology that is based on a pure combinatorial
circuitry. In which, the Galois inverse of elements in
[attachment=53082]
Abstract
In this work, we derive three novel composite field arithmetic
(CFA) Advanced Encryption Standard (AES) S-boxes of the field. The best construction is selected after a sequence of
algorithmic and architectural optimization processes. Furthermore, for
each composite field constructions, there exists eight possible isomorphic
mappings. Therefore, after the exploitation of a new common subexpression
elimination algorithm, the isomorphic mapping that results in the
minimal implementation area cost is chosen. High throughput hardware
implementations of our proposed CFA AES S-boxes are reported towards
the end of this paper. Through the exploitation of both algebraic normal
form and seven stages fine-grained pipelining, our best case achieves a
throughput 3.49 Gbps on a Cyclone II EP2C5T144C6 field-programmable
gate array.
INTRODUCTION
The Advanced Encryption Standard (AES) is an encryption standard
chosen by the National Institute of Standards and Technology (NIST) in
2001, which has its origin in the Rijndael block cipher. Several studies
in the area had identified the nonlinear SubBytes transformation as the
major bottleneck in achieving both small area and high speed VLSI
AES implementations [1].
This brief presents a methodology that is based on a pure combinatorial
circuitry. In which, the Galois inverse of elements in