07-05-2013, 12:51 PM
The 8086 Microprocessor
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1.Draw the pin diagram of 8086.
Ans. There would be two pin diagrams—one for MIN mode and the other for MAX mode of
8086, shown in Figs. 11.1 and 11.2 respectively. The pins that differ with each other in
the two modes are from pin-24 to pin-31 (total 8 pins).
2. What is the technology used in 8086 μP?
Ans. It is manufactured using high performance metal-oxide semiconductor (HMOS)
technology. It has approximately 29,000 transistors and housed in a 40-pin DIP package.
3. Mention and explain the modes in which 8086 can operate.
Ans. 8086 μP can operate in two modes—MIN mode and MAX mode.
When MN/MX pin is high, it operates in MIN mode and when low, 8086 operates
in MAX mode.
4. Distinguish between the lower sixteen address lines from the upper four.
Ans. Both the lower sixteen address lines (AD0 − AD1 5 ) and the upper four address lines
(A16 /S3 − A19 /S6 ) are multiplexed.
During T1, the lower sixteen lines carry address (A0 − A15 ) , while during T2, T3 and
T4 they carry data.
Similarly during T1, the upper four lines carry address (A16– A19), while during T2,
T3 and T4 , they carry status signals.
5. In how many modes the minimum-mode signal can be divided?
Ans. In the MIN mode, the signals can be divided into the following basic groups: address/data
bus, status, control, interrupt and DMA.
6. Tabulate the common signals, Minimum mode signals and Maximum mode
signals. Also mention their functions and types.
Ans. Table 11.1 shows the common signals, Minimum mode signals and the Maximum mode
signals, along with the functions of each and their types.
7. Mention the different varieties of 8086 and their corresponding speeds.
Ans. The following shows the different varieties of 8086 available and their corresponding
speeds.
Types Speeds
8086 5 MHz
8086–1 10 MHz
8086–2 8 MHz
8. Mention (a) the address capability of 8086 and (b) how many I/O lines can be
accessed by 8086.
Ans. 8086 addresses via its A0–A19 address lines. Hence it can address 220 = 1MB memory.
Address lines A0 to A15 are used for accessing I/O’s. Thus, 8086 can access 216 = 64
KB of I/O’s.
9. What is meant by microarchitecture of 8086?
Ans. The individual building blocks of 8086 that, as a whole, implement the software and
hardware architecture of 8086. Because of incorporation of additional features being
necessitated by higher performance, the microarchitecture of 8086 or for that matter any
microprocessor family, evolves over time.
10. Draw and discuss the architecture of 8086. Mention the jobs performed by BIU
and EU.
Ans. The architecture of 8086 is shown below in Fig. 11.3. It has got two separate functional
units—Bus Interface Unit (BIU) and Execution Unit (EU).
8086 architecture employs parallel processing—i.e., both the units (BIU and EU) work
at the same time. This is Unlike 8085 in which Sequential fetch and execute operations
take place. Thus in case of 8086, efficient use of system bus takes place and higher
performance (because of reduced instruction time) is ensured.
BIU has segment registers, instruction pointer, address generation and bus
control logic block, instruction queue while the EU has general purpose registers,
ALU, control unit, instruction register, flag (or status) register.
The main jobs performed by BIU are:
BIU is the 8086’s interface to the outside world, i.e., all External bus operations
are done by BIU.
It does the job of instruction fetching, reading/writing of data/operands for memory
and also the inputting/outputting of data for peripheral devices.
It does the job of filling the instruction queue.
Does the job of address generation.
[attachment=53511]
1.Draw the pin diagram of 8086.
Ans. There would be two pin diagrams—one for MIN mode and the other for MAX mode of
8086, shown in Figs. 11.1 and 11.2 respectively. The pins that differ with each other in
the two modes are from pin-24 to pin-31 (total 8 pins).
2. What is the technology used in 8086 μP?
Ans. It is manufactured using high performance metal-oxide semiconductor (HMOS)
technology. It has approximately 29,000 transistors and housed in a 40-pin DIP package.
3. Mention and explain the modes in which 8086 can operate.
Ans. 8086 μP can operate in two modes—MIN mode and MAX mode.
When MN/MX pin is high, it operates in MIN mode and when low, 8086 operates
in MAX mode.
4. Distinguish between the lower sixteen address lines from the upper four.
Ans. Both the lower sixteen address lines (AD0 − AD1 5 ) and the upper four address lines
(A16 /S3 − A19 /S6 ) are multiplexed.
During T1, the lower sixteen lines carry address (A0 − A15 ) , while during T2, T3 and
T4 they carry data.
Similarly during T1, the upper four lines carry address (A16– A19), while during T2,
T3 and T4 , they carry status signals.
5. In how many modes the minimum-mode signal can be divided?
Ans. In the MIN mode, the signals can be divided into the following basic groups: address/data
bus, status, control, interrupt and DMA.
6. Tabulate the common signals, Minimum mode signals and Maximum mode
signals. Also mention their functions and types.
Ans. Table 11.1 shows the common signals, Minimum mode signals and the Maximum mode
signals, along with the functions of each and their types.
7. Mention the different varieties of 8086 and their corresponding speeds.
Ans. The following shows the different varieties of 8086 available and their corresponding
speeds.
Types Speeds
8086 5 MHz
8086–1 10 MHz
8086–2 8 MHz
8. Mention (a) the address capability of 8086 and (b) how many I/O lines can be
accessed by 8086.
Ans. 8086 addresses via its A0–A19 address lines. Hence it can address 220 = 1MB memory.
Address lines A0 to A15 are used for accessing I/O’s. Thus, 8086 can access 216 = 64
KB of I/O’s.
9. What is meant by microarchitecture of 8086?
Ans. The individual building blocks of 8086 that, as a whole, implement the software and
hardware architecture of 8086. Because of incorporation of additional features being
necessitated by higher performance, the microarchitecture of 8086 or for that matter any
microprocessor family, evolves over time.
10. Draw and discuss the architecture of 8086. Mention the jobs performed by BIU
and EU.
Ans. The architecture of 8086 is shown below in Fig. 11.3. It has got two separate functional
units—Bus Interface Unit (BIU) and Execution Unit (EU).
8086 architecture employs parallel processing—i.e., both the units (BIU and EU) work
at the same time. This is Unlike 8085 in which Sequential fetch and execute operations
take place. Thus in case of 8086, efficient use of system bus takes place and higher
performance (because of reduced instruction time) is ensured.
BIU has segment registers, instruction pointer, address generation and bus
control logic block, instruction queue while the EU has general purpose registers,
ALU, control unit, instruction register, flag (or status) register.
The main jobs performed by BIU are:
BIU is the 8086’s interface to the outside world, i.e., all External bus operations
are done by BIU.
It does the job of instruction fetching, reading/writing of data/operands for memory
and also the inputting/outputting of data for peripheral devices.
It does the job of filling the instruction queue.
Does the job of address generation.