13-05-2013, 02:27 PM
A Review of Low Cost Multiplier Using CORDIC Subsystem
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Abstract
CORDIC subsystem is used in multiplication of complex numbers which is used in various applications such as radar, sonar etc. Including serial multiplier this paper attempts to analyses the cordic based complex multiplier having two main architectures, one is recursive and other is pipelined. This multiplication of a complex number (containing real and imaginary parts) to a number in rectangular form results the product containing the real and imaginary parts.
INTRODUCTION
Structure of the most efficient multiplier will vary depending on the throughput requirement of the application. In this paper we discuss about many structures to perform the multiplication operation (real and complex numbers).
The multiplication operation of real quantity is performed with the help of simple serial multiplier [10] or parallel multiplier [4]-[5]. The serial multiplier implements the multiplication in n cycles for a n×n bit multipliers with least hardware [10]. The n×n bit multiplier requires a 2n bit adders and shift registers to implement the multiplication. Parallel multipliers are commonly used in high performance digital signal processors [3],[4]. The simplest way of implementing parallel multiplier is to generate all partial products and reduce them to rows of carry and sum signals. The final step is the addition of the generated carry and sum signals. Booth encoding [1, 3] is widely used in parallel multipliers to reduce the number of generated partial products.
MULTIPLIER STRUCTURES
Energy efficient serial and parallel multiplier structures are explored to see their stability in low and ultra low power design. The serial multipliers are commonly used in high performance digital signal processors. They require more hardware compare to the serial multiplier in order to provide performance improvements.
A. Serial Multiplier
It works on the principle of shift and add algorithm. Output is generated in 16- clock cycles. A 32- bit register is used to feed the current sum to the input of adder over an AND operation. RST input is designed to reset internal residue of the circuit before the start of new multiplication operation. The Block Diagram of serial multiplier
Recursive Cordic Multiplier
The first complex number C is introduced in its rectangular coordinate from, with a p-bit real-axis component C_R data word at first input and p-bit imaginary axis component C_I data word at second input of a multiplier` Other complex number B is introduced in polar coordinate form, with a p-bit data word for a magnitude ׀B׀ component at input of both scalar data multiplier, with an angle ∅ component data word provided at input to PLA. The complex multiplier output provides separate real and imaginary rectangular form terms A_R and A_I. The first and second sign select, the sign but not magnitude of input data is either unaffected or inverted dependent upon the state of sign select binary control signal at a sign select inputs. The mux output is connected to either original polarity input or inverted polarity input. The binary state of sign select signal is determined by a sign control. One PLA input can receive from input, the clk pulses while the second PLA input can receive phase angle ∅ information for the second complex quantity.
CONCLUSION
The parallel multiplier will be more energy efficient than the serial multiplier in low throughput design. Complex multiplication is required in many communication and signal processing systems. By using CORDIC, we find the product of two complex numbers. Recursive and pipelined rotators are used for multiplication complex quantities. Keeping in mind the complexity and cost, the enhancement in speed is required. For high throughput applications, efficient pipelined architectures with multiple cordic units could be developed to take the advantage of pipelineability of cordic.
[attachment=53802]
Abstract
CORDIC subsystem is used in multiplication of complex numbers which is used in various applications such as radar, sonar etc. Including serial multiplier this paper attempts to analyses the cordic based complex multiplier having two main architectures, one is recursive and other is pipelined. This multiplication of a complex number (containing real and imaginary parts) to a number in rectangular form results the product containing the real and imaginary parts.
INTRODUCTION
Structure of the most efficient multiplier will vary depending on the throughput requirement of the application. In this paper we discuss about many structures to perform the multiplication operation (real and complex numbers).
The multiplication operation of real quantity is performed with the help of simple serial multiplier [10] or parallel multiplier [4]-[5]. The serial multiplier implements the multiplication in n cycles for a n×n bit multipliers with least hardware [10]. The n×n bit multiplier requires a 2n bit adders and shift registers to implement the multiplication. Parallel multipliers are commonly used in high performance digital signal processors [3],[4]. The simplest way of implementing parallel multiplier is to generate all partial products and reduce them to rows of carry and sum signals. The final step is the addition of the generated carry and sum signals. Booth encoding [1, 3] is widely used in parallel multipliers to reduce the number of generated partial products.
MULTIPLIER STRUCTURES
Energy efficient serial and parallel multiplier structures are explored to see their stability in low and ultra low power design. The serial multipliers are commonly used in high performance digital signal processors. They require more hardware compare to the serial multiplier in order to provide performance improvements.
A. Serial Multiplier
It works on the principle of shift and add algorithm. Output is generated in 16- clock cycles. A 32- bit register is used to feed the current sum to the input of adder over an AND operation. RST input is designed to reset internal residue of the circuit before the start of new multiplication operation. The Block Diagram of serial multiplier
Recursive Cordic Multiplier
The first complex number C is introduced in its rectangular coordinate from, with a p-bit real-axis component C_R data word at first input and p-bit imaginary axis component C_I data word at second input of a multiplier` Other complex number B is introduced in polar coordinate form, with a p-bit data word for a magnitude ׀B׀ component at input of both scalar data multiplier, with an angle ∅ component data word provided at input to PLA. The complex multiplier output provides separate real and imaginary rectangular form terms A_R and A_I. The first and second sign select, the sign but not magnitude of input data is either unaffected or inverted dependent upon the state of sign select binary control signal at a sign select inputs. The mux output is connected to either original polarity input or inverted polarity input. The binary state of sign select signal is determined by a sign control. One PLA input can receive from input, the clk pulses while the second PLA input can receive phase angle ∅ information for the second complex quantity.
CONCLUSION
The parallel multiplier will be more energy efficient than the serial multiplier in low throughput design. Complex multiplication is required in many communication and signal processing systems. By using CORDIC, we find the product of two complex numbers. Recursive and pipelined rotators are used for multiplication complex quantities. Keeping in mind the complexity and cost, the enhancement in speed is required. For high throughput applications, efficient pipelined architectures with multiple cordic units could be developed to take the advantage of pipelineability of cordic.