14-05-2013, 02:56 PM
Design of 8-bit microprocessor using Verilog (SAP-1 architecture)
[attachment=53880]
Introduction
The Simple-As-Possible (SAP)-1 computer is a very basic model of a microprocessor explained by
Albert Paul Malvino1. The SAP-1 design contains the basic necessities for a functional
Microprocessor. Its primary purpose is to develop a basic understanding of how a microprocessor
works, interacts with memory and other parts of the system like input and output. The
instruction set is very limited and is simple.
Machine cycle and Instruction cycle
SAP1 has six T-states (three fetch and three execute cycles) reserved for each instruction. Not all
instructions require all the six T-states for execution. The unused T- state is marked as No
Operation (NOP) cycle.
Each T-state is called a machine cycle for SAP1. A ring counter is used to generate a T-state at
every falling edge of clock pulse. The ring counter output is reset after the 6th T-state.
Discussion
The design of modules like Program Counter, Input and MAR, RAM, Instruction Register,
Accumulator, Adder-Subtracter, B register, Output register was easy as similar designs were already
done in Lab assignments.
The most complicated part was the design of Controller/Sequencer(C/S). The first problem we
faced arose due to failure to understand about the settling times for data lines. We tried to check the
data lines at the instant it changed and hence we got the old value of the data line. This problem was
resolved by adding a 1ms delay ( #1; ). The second problem we faced in designing C/S was
“Maximum HDL code reached”. We deleted the code for test bench of other modules to decrease
the size of our project. This was probably the limitation of beta version of Silos workbench
(Silos2001.120) which we used in this project for coding and testing of Verilog code for SAP1
computer.
The task of synchronizing each block was also very complicated. The presence of a shared bus
(WBUS) also caused several complications during the design.
Conclusion
We became familiar with the working of a 8-bit microprocessor and the way each module
contributes to the overall functioning of the computer. Although the concept of SAP1 is very
simple, the knowledge gained while designing it can be extended to design of more complex
microprocessors.
We successfully designed a 8-bit microprocessor based on SAP1 architecture and verified it's
operations in Verilog.
[attachment=53880]
Introduction
The Simple-As-Possible (SAP)-1 computer is a very basic model of a microprocessor explained by
Albert Paul Malvino1. The SAP-1 design contains the basic necessities for a functional
Microprocessor. Its primary purpose is to develop a basic understanding of how a microprocessor
works, interacts with memory and other parts of the system like input and output. The
instruction set is very limited and is simple.
Machine cycle and Instruction cycle
SAP1 has six T-states (three fetch and three execute cycles) reserved for each instruction. Not all
instructions require all the six T-states for execution. The unused T- state is marked as No
Operation (NOP) cycle.
Each T-state is called a machine cycle for SAP1. A ring counter is used to generate a T-state at
every falling edge of clock pulse. The ring counter output is reset after the 6th T-state.
Discussion
The design of modules like Program Counter, Input and MAR, RAM, Instruction Register,
Accumulator, Adder-Subtracter, B register, Output register was easy as similar designs were already
done in Lab assignments.
The most complicated part was the design of Controller/Sequencer(C/S). The first problem we
faced arose due to failure to understand about the settling times for data lines. We tried to check the
data lines at the instant it changed and hence we got the old value of the data line. This problem was
resolved by adding a 1ms delay ( #1; ). The second problem we faced in designing C/S was
“Maximum HDL code reached”. We deleted the code for test bench of other modules to decrease
the size of our project. This was probably the limitation of beta version of Silos workbench
(Silos2001.120) which we used in this project for coding and testing of Verilog code for SAP1
computer.
The task of synchronizing each block was also very complicated. The presence of a shared bus
(WBUS) also caused several complications during the design.
Conclusion
We became familiar with the working of a 8-bit microprocessor and the way each module
contributes to the overall functioning of the computer. Although the concept of SAP1 is very
simple, the knowledge gained while designing it can be extended to design of more complex
microprocessors.
We successfully designed a 8-bit microprocessor based on SAP1 architecture and verified it's
operations in Verilog.