15-05-2013, 12:48 PM
Reliable and Cost Effective Anti-coll ision Technique for RFID UHF Tag
[attachment=53922]
Abstract
This paper presents a proposed Reliable and Cost
Effective Anti-collision technique (RCEAT) for Radio
Frequency Identification (RFID) Class 0 UHF tag. The
RCEAT architecture consists of two main subsystems;
PreRCEAT and PostRCEAT. The PreRCEAT
subsystem is to detect any error in the incoming
messages. Then the identification bit (ID) of the no error
packet will be fed to the next subsystem. The
PostRCEAT subsystem is to identify the tag by using
the proposed Fast-search Lookup Table. The proposed
system is designed using Verilog HDL. The system is
simulated using Modelsim and synthesized using
Xilinix Synthesis Technology. The system has been
successfully implemented in hardware using Field
Programmable Grid Array (FPGA) Virtex II. The
output waveforms from the FPGA have been tested on
the Tektronix Logic Analyzer for real time verification.
Finally the RCEAT architecture is resynthesized using
Application Specific Integrated Circuit (ASIC)
technology for on-chip implementation. This technology
consists of 0.18 μm Library, Synopsys Compiler and
tools. From the hardware verification results, it shows
that the proposed RCEAT system enables to identify the
tags without error at the maximum operating frequency
of 180MHz. The system consumes 7.578 mW powers,
occupies 6,041 gates and 0.0375 mm2 area with Data
arrival time of 2.31 ns.
Introduction
In the data management system a significant role of the
Data link layer is to convert the unreliable physical link
between reader and tag into a reliable link. Therefore,
the RFID system employs the Cyclic Redundancy Check
(CRC) as an error detection scheme. The CRC
calculation consists of an iterative process involving
Exclusive-ORs and shift register which is executed
much faster in hardware compare in software [9].
In addition for reader to communicate with the
multiple tags, an anti-collision technique is required.
The technique is to coordinate the communication
between the reader and the tags. The common
deterministic anti-collision techniques are based on the
Tree algorithm such as the Binary Tree and the Query
Tree algorithms [1]-[4].
Methodology
In our proposed RCEAT the frame consists of slots
and each slot (column) is divided into four minislots
(rows). Therefore in each slot, four tags are allowed for
contending the minislots. The RCEAT will identify
these four tags using the proposed Lookup table. The
uniqueness of this proposed technique is reducing the
tag identification time in the Binary Tree. The existing
tags are divided into four in each Read cycle to reduce
the required iterations and thus faster the tag
identification. This proposed technique does not require
the tag to remember the instructions from the reader
during the identification process. Thus the tag is treated
as an address carrying device only and memory-less tag
can be designed which requires very low power. The
RCEAT identification methodology is shown in Fig. 1.
In RCEAT, bidirectional communications are involved,
from the reader to the tag (Downlink) and from the tag
to the reader (Uplink). When the reader detects there are
tags exist in its interrogation zone, it will power these
tags. Then the reader sends the Select-group command
based on the tag Prefix or Object Class (OC). The
selected tags group will move to the Ready state. Next
the Reader transmits Reset signals and its frame. After
that the frame is transmitted back to the reader, column
by column starting with the first column. This
compensates the time required for transmitting the
packet to the reader. Therefore for every Read cycle,
there are always available packets at the reader waiting
for identification.
Architecture
The RCEAT architecture consists of two subsystem;
PreCLART and PostRCEAT (Fig. 4). In the
PreRCEAT, the received messages are fed into the
CRC-remover module. These received messages will be
separated into two; the received packet and the received
CRC. These packet and CRC are sent to the CRCchecker
module for verification process. The CRCchecker
module recalculated the CRC of the received
packet. Then, this calculated CRC is compared with the
received CRC. If the values are same, means no error,
the status-bit is set to its original value i.e. zero.
Simulation results
Verilog HDL codes for the RCEAT architecture have
been successfully simulated and verified using the
ModelSim XE II/Starter 5.7g tool. The following will
discuss the Behavioral simulation waveforms for the
selected ports in the RCEAT system as shown in Fig. 2.
At the first Read cycle, for the received messages of
000C8584416, 0000550A516, 00010123116, and
0EA6093DF16, the recalculated CRC of these messages
are 584416, 50A516, 123116, and 93DF16 respectively. As
a result, the calculated CRCs are equal to the received
CRCs which are represented by the four bit of the least
significant bit (LSB) of the messages. Since there are no
errors in the received messages, the Status-bit of the
packets are set to zero, which are represented by the
MSB of the packets; 000C816, 0000516, 0001016 and
0EA6016 respectively. Finally, the ID of these packets
will be fed simultaneously to the PostRCEAT
subsystem.
Implementation and verification
The RCEAT architecture has been implemented in
hardware using the Field Programmable Grid Array
(FPGA) model Virtex II Xc2v250. The output
waveforms from the FPGA have been displayed using
the Tektronix Logic Analyzer model TLA 5201 for real
time verification. From the result, it shows that the
system still enables to identify the tags without errors at
the operating frequency of 180 MHz. Fig. 3 shows the
FPGA output and its equivalent place and route
simulation result at this frequency. For examples for the
first Read cycle the identified tags are 03E516, 0F9016,
18E016 and 1FC816 as marked by a circle.
Conclusions
A proposed Reliable and Cost Effective Anti-collision
technique (RCEAT) is designed to achieve a reliable and
cost effective identification technique of the tag. The
RCEAT architecture consists of two main subsystems;
PreRCEAT checks error in the incoming packets using
the CRC scheme. PostRCEAT identifies the error free
packets using Binary Tree based technique. The
architecture has been synthesized using Xilinix
Synthesis Technology (XST). The RCEAT architecture
also has been successfully implemented in hardware
using FPGA model Virtex II Xc2v250. The FPGA
outputs have been verified in real time using Tektronix
Logic Analyzer model TLA 520. Finally on chip
verification has been done using 0.18 μm Silterra
Library, Synopsys Compiler and tools. The result
shows that the architecture has smaller cell area, power
consumption and number of gates. Therefore minimize
the implementation and operating costs.
[attachment=53922]
Abstract
This paper presents a proposed Reliable and Cost
Effective Anti-collision technique (RCEAT) for Radio
Frequency Identification (RFID) Class 0 UHF tag. The
RCEAT architecture consists of two main subsystems;
PreRCEAT and PostRCEAT. The PreRCEAT
subsystem is to detect any error in the incoming
messages. Then the identification bit (ID) of the no error
packet will be fed to the next subsystem. The
PostRCEAT subsystem is to identify the tag by using
the proposed Fast-search Lookup Table. The proposed
system is designed using Verilog HDL. The system is
simulated using Modelsim and synthesized using
Xilinix Synthesis Technology. The system has been
successfully implemented in hardware using Field
Programmable Grid Array (FPGA) Virtex II. The
output waveforms from the FPGA have been tested on
the Tektronix Logic Analyzer for real time verification.
Finally the RCEAT architecture is resynthesized using
Application Specific Integrated Circuit (ASIC)
technology for on-chip implementation. This technology
consists of 0.18 μm Library, Synopsys Compiler and
tools. From the hardware verification results, it shows
that the proposed RCEAT system enables to identify the
tags without error at the maximum operating frequency
of 180MHz. The system consumes 7.578 mW powers,
occupies 6,041 gates and 0.0375 mm2 area with Data
arrival time of 2.31 ns.
Introduction
In the data management system a significant role of the
Data link layer is to convert the unreliable physical link
between reader and tag into a reliable link. Therefore,
the RFID system employs the Cyclic Redundancy Check
(CRC) as an error detection scheme. The CRC
calculation consists of an iterative process involving
Exclusive-ORs and shift register which is executed
much faster in hardware compare in software [9].
In addition for reader to communicate with the
multiple tags, an anti-collision technique is required.
The technique is to coordinate the communication
between the reader and the tags. The common
deterministic anti-collision techniques are based on the
Tree algorithm such as the Binary Tree and the Query
Tree algorithms [1]-[4].
Methodology
In our proposed RCEAT the frame consists of slots
and each slot (column) is divided into four minislots
(rows). Therefore in each slot, four tags are allowed for
contending the minislots. The RCEAT will identify
these four tags using the proposed Lookup table. The
uniqueness of this proposed technique is reducing the
tag identification time in the Binary Tree. The existing
tags are divided into four in each Read cycle to reduce
the required iterations and thus faster the tag
identification. This proposed technique does not require
the tag to remember the instructions from the reader
during the identification process. Thus the tag is treated
as an address carrying device only and memory-less tag
can be designed which requires very low power. The
RCEAT identification methodology is shown in Fig. 1.
In RCEAT, bidirectional communications are involved,
from the reader to the tag (Downlink) and from the tag
to the reader (Uplink). When the reader detects there are
tags exist in its interrogation zone, it will power these
tags. Then the reader sends the Select-group command
based on the tag Prefix or Object Class (OC). The
selected tags group will move to the Ready state. Next
the Reader transmits Reset signals and its frame. After
that the frame is transmitted back to the reader, column
by column starting with the first column. This
compensates the time required for transmitting the
packet to the reader. Therefore for every Read cycle,
there are always available packets at the reader waiting
for identification.
Architecture
The RCEAT architecture consists of two subsystem;
PreCLART and PostRCEAT (Fig. 4). In the
PreRCEAT, the received messages are fed into the
CRC-remover module. These received messages will be
separated into two; the received packet and the received
CRC. These packet and CRC are sent to the CRCchecker
module for verification process. The CRCchecker
module recalculated the CRC of the received
packet. Then, this calculated CRC is compared with the
received CRC. If the values are same, means no error,
the status-bit is set to its original value i.e. zero.
Simulation results
Verilog HDL codes for the RCEAT architecture have
been successfully simulated and verified using the
ModelSim XE II/Starter 5.7g tool. The following will
discuss the Behavioral simulation waveforms for the
selected ports in the RCEAT system as shown in Fig. 2.
At the first Read cycle, for the received messages of
000C8584416, 0000550A516, 00010123116, and
0EA6093DF16, the recalculated CRC of these messages
are 584416, 50A516, 123116, and 93DF16 respectively. As
a result, the calculated CRCs are equal to the received
CRCs which are represented by the four bit of the least
significant bit (LSB) of the messages. Since there are no
errors in the received messages, the Status-bit of the
packets are set to zero, which are represented by the
MSB of the packets; 000C816, 0000516, 0001016 and
0EA6016 respectively. Finally, the ID of these packets
will be fed simultaneously to the PostRCEAT
subsystem.
Implementation and verification
The RCEAT architecture has been implemented in
hardware using the Field Programmable Grid Array
(FPGA) model Virtex II Xc2v250. The output
waveforms from the FPGA have been displayed using
the Tektronix Logic Analyzer model TLA 5201 for real
time verification. From the result, it shows that the
system still enables to identify the tags without errors at
the operating frequency of 180 MHz. Fig. 3 shows the
FPGA output and its equivalent place and route
simulation result at this frequency. For examples for the
first Read cycle the identified tags are 03E516, 0F9016,
18E016 and 1FC816 as marked by a circle.
Conclusions
A proposed Reliable and Cost Effective Anti-collision
technique (RCEAT) is designed to achieve a reliable and
cost effective identification technique of the tag. The
RCEAT architecture consists of two main subsystems;
PreRCEAT checks error in the incoming packets using
the CRC scheme. PostRCEAT identifies the error free
packets using Binary Tree based technique. The
architecture has been synthesized using Xilinix
Synthesis Technology (XST). The RCEAT architecture
also has been successfully implemented in hardware
using FPGA model Virtex II Xc2v250. The FPGA
outputs have been verified in real time using Tektronix
Logic Analyzer model TLA 520. Finally on chip
verification has been done using 0.18 μm Silterra
Library, Synopsys Compiler and tools. The result
shows that the architecture has smaller cell area, power
consumption and number of gates. Therefore minimize
the implementation and operating costs.