01-06-2013, 02:40 PM
Memory interface
[attachment=54626]
Memory is a device to store data
To interfacing with memories, there must be:
address bus, data bus and control signals (chip enable, output enable etc)
To study memory interface, we must learn how to connect memory chips to the microprocessor and how to write/read data from the memory
Different kinds of memory chips will also be introduced
Introduction
For the 8086 microprocessor, there are two modes: minimum and maximum
Under different modes, the memory interface is not the same
In the minimum mode, 8086 processor is connected to the external memory block directly
In the maximum mode, a Bus controller is needed
The bus controller will issue the required control signal to drive the memory block
Address space and data organization
Memory is organized as 8-bit bytes (byte as the basic unit)
To address a word then 2 consecutive bytes are used, lower addressed byte is the LSB (Least Significant Byte) and the higher-addressed byte is the MSB (Most Significant Byte)
Words of data can be stored at even, or odd address boundaries
Memory addressing
The address bit A0 of the LSB can be used to determine the address boundary. If A0 is 0 then we have an even address, or aligned
If A0 is odd then we have odd-boundary
Example: 0001H is an odd-boundary address
Data type
Double word (32-bit) will be stored in 4 consecutive locations
When double word is used?
Double word can be used as a pointer that is used to address data or code outside the current segment
For a double word, the higher WORD stores the segment address, the lower WORD stores the offset
Hardware organization
In hardware, the 1M bytes memory is implemented as two independent 512K-byte banks
Low (even) bank, and the high (odd) bank
Data from low bank use data lines 0-7
Data from high bank use data lines 8-15
Signal A0 enables the low bank
Signal /BHE enables the high bank
/BHE is active low
How many address lines are required in order to access 512K locations? (Ans. 19)
Memory Read Operation
To read a ROM, we need to issue the proper address
There is a delay between address inputs and data outputs
The access time (tACC), chip enable time (tCE), and chip deselect time (tDF) are important timing properties
You need these information for developing a real computer system!
Random access memory (RAM)
Data can be read as well as written into the memory chip
Static ram (SRAM) – data remains valid as long as the power is ON
Dynamic RAM (DRAM) – needs to periodically restore (recharge) the data in each storage location by addressing them
If storage nodes are not recharged at regular intervals of time, data would be lost. This process is called refreshing
RAM write operation
Refer to timing diagram
Data should now ready and must be valid for tDW (data valid to end of write)
Data should remain valid (tDH) after the write
A short recovery period (tWR) takes place after /WE returns to 1 before the write cycle is complete (address is removed)
[attachment=54626]
Memory is a device to store data
To interfacing with memories, there must be:
address bus, data bus and control signals (chip enable, output enable etc)
To study memory interface, we must learn how to connect memory chips to the microprocessor and how to write/read data from the memory
Different kinds of memory chips will also be introduced
Introduction
For the 8086 microprocessor, there are two modes: minimum and maximum
Under different modes, the memory interface is not the same
In the minimum mode, 8086 processor is connected to the external memory block directly
In the maximum mode, a Bus controller is needed
The bus controller will issue the required control signal to drive the memory block
Address space and data organization
Memory is organized as 8-bit bytes (byte as the basic unit)
To address a word then 2 consecutive bytes are used, lower addressed byte is the LSB (Least Significant Byte) and the higher-addressed byte is the MSB (Most Significant Byte)
Words of data can be stored at even, or odd address boundaries
Memory addressing
The address bit A0 of the LSB can be used to determine the address boundary. If A0 is 0 then we have an even address, or aligned
If A0 is odd then we have odd-boundary
Example: 0001H is an odd-boundary address
Data type
Double word (32-bit) will be stored in 4 consecutive locations
When double word is used?
Double word can be used as a pointer that is used to address data or code outside the current segment
For a double word, the higher WORD stores the segment address, the lower WORD stores the offset
Hardware organization
In hardware, the 1M bytes memory is implemented as two independent 512K-byte banks
Low (even) bank, and the high (odd) bank
Data from low bank use data lines 0-7
Data from high bank use data lines 8-15
Signal A0 enables the low bank
Signal /BHE enables the high bank
/BHE is active low
How many address lines are required in order to access 512K locations? (Ans. 19)
Memory Read Operation
To read a ROM, we need to issue the proper address
There is a delay between address inputs and data outputs
The access time (tACC), chip enable time (tCE), and chip deselect time (tDF) are important timing properties
You need these information for developing a real computer system!
Random access memory (RAM)
Data can be read as well as written into the memory chip
Static ram (SRAM) – data remains valid as long as the power is ON
Dynamic RAM (DRAM) – needs to periodically restore (recharge) the data in each storage location by addressing them
If storage nodes are not recharged at regular intervals of time, data would be lost. This process is called refreshing
RAM write operation
Refer to timing diagram
Data should now ready and must be valid for tDW (data valid to end of write)
Data should remain valid (tDH) after the write
A short recovery period (tWR) takes place after /WE returns to 1 before the write cycle is complete (address is removed)