20-06-2013, 04:36 PM
Video/Imaging Fixed-Point Digital Signal Processor
[attachment=55770]
INTRODUCTION
The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-point
DSP generation in the TMS320C6000™ DSP platform. The TMS320DM642 (DM642) device is based on
the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW)
architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice
for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.
With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the
DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The
DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of
array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length
and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic
units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units
include new instructions to accelerate the performance in video and imaging applications and extend the
parallelism of the VelociTI™ architecture. The DM642 can produce four 16-bit multiply-accumulates
(MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for
a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory,
and additional on-chip peripherals similar to the other C6000™ DSP platform devices.
The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals.
The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is
a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory
space that is shared between program and data space. L2 memory can be configured as mapped
memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a
10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO
interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated
circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose
timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component
interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event
generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of
interfacing to synchronous and asynchronous memories and peripherals.
CPU (DSP Core) Description
The CPU fetches VelociTI™ advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to
eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW
architecture features controls by which all eight units do not have to be supplied with instructions if they
are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs
to the same execute packet as the previous instruction, or whether it should be executed in the following
clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute
packets can vary in size. The variable-length execute packets are a key memory-saving feature,
distinguishing the C64x CPUs from other VLIW architectures. The C64x™ VelociTI.2™ extensions add
enhancements to the TMS320C62x™ DSP VelociTI™ architecture.
Bootmode
The DM642 device resets using the active-low signal RESET. While RESET is low, the device is held in
reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics
and states of device pins during reset. The release of RESET starts the processor running with the
prescribed device configuration and boot mode.
[attachment=55770]
INTRODUCTION
The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-point
DSP generation in the TMS320C6000™ DSP platform. The TMS320DM642 (DM642) device is based on
the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW)
architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice
for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.
With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the
DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The
DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of
array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length
and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic
units (ALUs)—with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units
include new instructions to accelerate the performance in video and imaging applications and extend the
parallelism of the VelociTI™ architecture. The DM642 can produce four 16-bit multiply-accumulates
(MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for
a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory,
and additional on-chip peripherals similar to the other C6000™ DSP platform devices.
The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals.
The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is
a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory
space that is shared between program and data space. L2 memory can be configured as mapped
memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a
10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO
interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated
circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose
timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component
interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event
generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of
interfacing to synchronous and asynchronous memories and peripherals.
CPU (DSP Core) Description
The CPU fetches VelociTI™ advanced very-long instruction words (VLIWs) (256 bits wide) to supply up to
eight 32-bit instructions to the eight functional units during every clock cycle. The VelociTI™ VLIW
architecture features controls by which all eight units do not have to be supplied with instructions if they
are not ready to execute. The first bit of every 32-bit instruction determines if the next instruction belongs
to the same execute packet as the previous instruction, or whether it should be executed in the following
clock as a part of the next execute packet. Fetch packets are always 256 bits wide; however, the execute
packets can vary in size. The variable-length execute packets are a key memory-saving feature,
distinguishing the C64x CPUs from other VLIW architectures. The C64x™ VelociTI.2™ extensions add
enhancements to the TMS320C62x™ DSP VelociTI™ architecture.
Bootmode
The DM642 device resets using the active-low signal RESET. While RESET is low, the device is held in
reset and is initialized to the prescribed reset state. Refer to reset timing for reset timing characteristics
and states of device pins during reset. The release of RESET starts the processor running with the
prescribed device configuration and boot mode.