25-06-2013, 01:57 PM
INTERFACING ICs
[attachment=55977]
Interfacing chips
Programmable Communication Interface – PCI (8251)
Programmable Interval Timer (8253)
Programmable Peripheral Interfacing - PPI (8255)
Programmable DMA controller (8257)
Programmable Interrupt Controller (8259)
Programmable Keyboard Display Interface (8279)
Synchronous Vs Asynchronous
Asynchronous transfer does not require clock signal.
However, it transfers extra bits(start bits and stop bits) during data communication.
Synchronous does not transfer extra bits. However, it requires clock signal.
8251 USART
The 8251 USART (Universal Synchronous Asynchronous Receiver Transmitter) is capable of implementing either an asynchronous or synchronous serial data communication.
As a peripheral device of a microcomputer system, the 8251 receives parallel data from the CPU and transmits serial data after conversion.
This device also receives serial data from the outside and transmits parallel data to the CPU after conversion.
Pin Description
D0 - D7 - This is bidirectional data bus which receive control words and transmits data from the CPU and sends status words and received data to CPU.
RESET - A "High" on this input forces the 8251 into "reset status”. The min. reset width is six clock inputs during the operating status of CLK.
CLK - CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC.
WR - This is the "active low" input terminal which receives a signal for writing transmit data and control words from the CPU into the 8251.
Pin Description
RD - This is the "active low" input terminal which receives a signal for reading receive data and status words from the 8251.
C/D - This is an input terminal which receives a signal for selecting data or command words and status words when the 8251 is accessed by the CPU.
CS - This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses.
8251 Initialization
Before the 8251 can be used to receiver or transmit characters, its mode control and command registers must be initialized.
The 8251 has only one address for a few control registers.
The only readable register is a status register. The other registers must be written in sequence.
Mode instruction word
Mode instruction is used for setting the function of the 8251.
Mode instruction will be in "wait for write" at either internal reset or external reset.
That is, the writing of a control word after resetting will be recognized as a "mode instruction.“
Items set by mode instruction are as follows:
Synchronous/asynchronous mode
Stop bit length (asynchronous mode)
Character length
Parity bit
Baud rate factor (asynchronous mode)
Internal/external synchronization (synchronous mode)
Number of synchronous characters (Synchronous mode)
Control Word Register
This internal register is used to write information to, prior to using the device.
This register is addressed when A0 and A1 inputs are logical 1's.
The data in the register controls the operation mode and the selection of either binary or BCD counting format.
The register can only be written to.
You can't read information from the register.
Direct memory access
Direct memory access (DMA) is a process in which an external device takes over the control of system bus from the CPU.
DMA is for high-speed data transfer from/to mass storage peripherals, e.g. harddisk drive, magnetic tape, CD-ROM, and sometimes video controllers.
The basic idea of DMA is to transfer blocks of data directly between memory and peripherals.
The data don’t go through the microprocessor but the data bus is occupied.
Basic process of DMA – Minimum Mode
The HOLD and HLDA pins are used to receive and acknowledge the hold request respectively.
Normally the CPU has full control of the system bus.
In a DMA operation, the peripheral takes over bus control temporarily.
Basic process of DMA – Maximum Mode
The RQ/GT1 and RQ/GT0 pins are used to issue DMA request and receive acknowledge signals.
Sequence of events of a typical DMA process:
Peripheral asserts one of the request pins, e.g. RQ/GT1 or RQ/GT0 (RQ/GT0 has higher priority)
8086 completes its current bus cycle and enters into a HOLD state.
8086 grants the right of bus control by asserting a grant signal via the same pin as the request signal.
DMA operation starts.
Upon completion of the DMA operation, the peripheral asserts the request/grant pin again to relinquish bus control.
DMA controller
A DMA controller interfaces with several peripherals that may request DMA.
The controller decides the priority of simultaneous DMA requests communicates with the peripheral and the CPU, and provides memory addresses for data transfer.
DMA controller commonly used with 8086 is the 8257/8237 programmable device.
The 8257/8237 is a 4-channel device.
Each channel is dedicated to a specific peripheral device and capable of addressing 64 K bytes section of memory.
Operation Command Words (OCWs)
After the Initialization Command Words (ICWs) are programmed into the 8259A, the chip is ready to accept interrupt requests at its input lines.
However, during the 8259A operation, a selection of algorithms can command the 8259A to operate in various modes through the Operation Command Words (OCWs).
Fully nested mode
This mode is entered after initialization unless another mode is programmed.
The interrupt requests are ordered in priority from 0 through 7 (0 highest).
When an interrupt is acknowledged the highest priority request is determined and its vector placed on the bus.
Additionally, a bit of the Interrupt Service register (ISO-7) is set.
This bit remains set until the microprocessor issues an End of Interrupt (EOI) command immediately before returning from the service routine
If AEOI (Automatic End of Interrupt) bit is set, until the trailing edge of the last INTA.
Polled mode
In Polled mode the INT output functions as it normally does.
The microprocessor should ignore this output.
This can be accomplished either by not connecting the INT output or by masking interrupts within the microprocessor, thereby disabling its interrupt input.
Service to devices is achieved by software using a Poll command.
The Poll command is issued by setting P = 1 in OCW3.
[attachment=55977]
Interfacing chips
Programmable Communication Interface – PCI (8251)
Programmable Interval Timer (8253)
Programmable Peripheral Interfacing - PPI (8255)
Programmable DMA controller (8257)
Programmable Interrupt Controller (8259)
Programmable Keyboard Display Interface (8279)
Synchronous Vs Asynchronous
Asynchronous transfer does not require clock signal.
However, it transfers extra bits(start bits and stop bits) during data communication.
Synchronous does not transfer extra bits. However, it requires clock signal.
8251 USART
The 8251 USART (Universal Synchronous Asynchronous Receiver Transmitter) is capable of implementing either an asynchronous or synchronous serial data communication.
As a peripheral device of a microcomputer system, the 8251 receives parallel data from the CPU and transmits serial data after conversion.
This device also receives serial data from the outside and transmits parallel data to the CPU after conversion.
Pin Description
D0 - D7 - This is bidirectional data bus which receive control words and transmits data from the CPU and sends status words and received data to CPU.
RESET - A "High" on this input forces the 8251 into "reset status”. The min. reset width is six clock inputs during the operating status of CLK.
CLK - CLK signal is used to generate internal device timing. CLK signal is independent of RXC or TXC.
WR - This is the "active low" input terminal which receives a signal for writing transmit data and control words from the CPU into the 8251.
Pin Description
RD - This is the "active low" input terminal which receives a signal for reading receive data and status words from the 8251.
C/D - This is an input terminal which receives a signal for selecting data or command words and status words when the 8251 is accessed by the CPU.
CS - This is the "active low" input terminal which selects the 8251 at low level when the CPU accesses.
8251 Initialization
Before the 8251 can be used to receiver or transmit characters, its mode control and command registers must be initialized.
The 8251 has only one address for a few control registers.
The only readable register is a status register. The other registers must be written in sequence.
Mode instruction word
Mode instruction is used for setting the function of the 8251.
Mode instruction will be in "wait for write" at either internal reset or external reset.
That is, the writing of a control word after resetting will be recognized as a "mode instruction.“
Items set by mode instruction are as follows:
Synchronous/asynchronous mode
Stop bit length (asynchronous mode)
Character length
Parity bit
Baud rate factor (asynchronous mode)
Internal/external synchronization (synchronous mode)
Number of synchronous characters (Synchronous mode)
Control Word Register
This internal register is used to write information to, prior to using the device.
This register is addressed when A0 and A1 inputs are logical 1's.
The data in the register controls the operation mode and the selection of either binary or BCD counting format.
The register can only be written to.
You can't read information from the register.
Direct memory access
Direct memory access (DMA) is a process in which an external device takes over the control of system bus from the CPU.
DMA is for high-speed data transfer from/to mass storage peripherals, e.g. harddisk drive, magnetic tape, CD-ROM, and sometimes video controllers.
The basic idea of DMA is to transfer blocks of data directly between memory and peripherals.
The data don’t go through the microprocessor but the data bus is occupied.
Basic process of DMA – Minimum Mode
The HOLD and HLDA pins are used to receive and acknowledge the hold request respectively.
Normally the CPU has full control of the system bus.
In a DMA operation, the peripheral takes over bus control temporarily.
Basic process of DMA – Maximum Mode
The RQ/GT1 and RQ/GT0 pins are used to issue DMA request and receive acknowledge signals.
Sequence of events of a typical DMA process:
Peripheral asserts one of the request pins, e.g. RQ/GT1 or RQ/GT0 (RQ/GT0 has higher priority)
8086 completes its current bus cycle and enters into a HOLD state.
8086 grants the right of bus control by asserting a grant signal via the same pin as the request signal.
DMA operation starts.
Upon completion of the DMA operation, the peripheral asserts the request/grant pin again to relinquish bus control.
DMA controller
A DMA controller interfaces with several peripherals that may request DMA.
The controller decides the priority of simultaneous DMA requests communicates with the peripheral and the CPU, and provides memory addresses for data transfer.
DMA controller commonly used with 8086 is the 8257/8237 programmable device.
The 8257/8237 is a 4-channel device.
Each channel is dedicated to a specific peripheral device and capable of addressing 64 K bytes section of memory.
Operation Command Words (OCWs)
After the Initialization Command Words (ICWs) are programmed into the 8259A, the chip is ready to accept interrupt requests at its input lines.
However, during the 8259A operation, a selection of algorithms can command the 8259A to operate in various modes through the Operation Command Words (OCWs).
Fully nested mode
This mode is entered after initialization unless another mode is programmed.
The interrupt requests are ordered in priority from 0 through 7 (0 highest).
When an interrupt is acknowledged the highest priority request is determined and its vector placed on the bus.
Additionally, a bit of the Interrupt Service register (ISO-7) is set.
This bit remains set until the microprocessor issues an End of Interrupt (EOI) command immediately before returning from the service routine
If AEOI (Automatic End of Interrupt) bit is set, until the trailing edge of the last INTA.
Polled mode
In Polled mode the INT output functions as it normally does.
The microprocessor should ignore this output.
This can be accomplished either by not connecting the INT output or by masking interrupts within the microprocessor, thereby disabling its interrupt input.
Service to devices is achieved by software using a Poll command.
The Poll command is issued by setting P = 1 in OCW3.