29-06-2013, 02:31 PM
A Seminar report On FPGA IN SPACE
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Abstract:
This report concerns FPGAs (Field Programmable Gate Arrays). The basic FPGA blocks, I/O, CLBs (Combinational Logic Blocks), and routing architecture, are discussed to impart a basic understanding of FPGA operation. The static RAM implementation method for the programming elements of FPGAs is briefly discussed. An in depth investigation of one common static RAM chip, the Xilinx XC5200, providing physical examples of I/O, CLB, and routing configurations used in industry, is included in the body of this report. Strengths and weaknesses of static RAMFPGAs are discussed in the conclusion.
Field-Programmable Gate Arrays (FPGAs) are pre-fabricated silicon devices that can be electrically programmed to become almost any kind of digital circuit or system [2]. They have many advantages over Application Specific Integrated Circuits (ASIC). ASICs are designed for specific application using CAD tools and fabricated at a foundry. Developing an ASIC takes very much time and is expensive. Furthermore, it is not possible to correct errors after fabrication. In contrast to ASICs, FPGAs are configured after fabrication and they also can be reconfigured. This is done with a hardware description language (HDL) which is compiled to a bit stream and downloaded to the FPGA. The disadvantages of FPGAs are that the same application needs more space (transistors) on chip and the application runs slower on a FPGA as modern as the ASIC counterpart. Due to the increase of transistor density FPGA were getting more powerful over the years. On the other hand the development of ASICs was getting slower and more expensive. Therefore FPGAs are increasingly applied to high performance embedded
systems.
History:
The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field programmable), however programmable logic was hard-wired between logic gates.In the late 1980s the Naval Surface Warfare Department funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.Some of the industry’s foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985.Xilinx co-founders Ross Freeman and Bernard Vonderschmitt invented the first commercially viable field programmable gate array in 1985 – the XC2064. The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market. The XC2064 boasted a mere 64 configurable logic blocks (CLBs), with two 3-input lookup tables (LUTs). More than 20 years later, Freeman was entered into the National Inventors Hall of Fame for his invention.Xilinx continued unchallenged and quickly growing from 1985 to the mid-1990s, when competitors sprouted up, eroding significant market-share. By 1993, Actel was serving about 18 percent of the market.The 1990s were an explosive period of time for FPGAs, both in sophistication and the volume of production. In the early 1990s, FPGAs were primarily used in telecommunications and networking. By the end of the decade, FPGAs found their way into consumer, automotive, and industrial applications.
Block Diagram Description:
Xilinx introduced Field programmable gate arrays, or FPGAs, in1985. Figure 1 is a conceptual model of an FPGA. FPGA are constructed of three basic elements: logic blocks, I/O cells, and
interconnection resources. A useful analogy for an FPGA is the layout of a city. The logic
blocks correspond to city blocks that are occupied by different businesses receiving
products from various suppliers within the city, just as the logic blocks receive data
from other logic blocks within the FPGA, and processing those products for consumption by
other firms or end users, just as logic block outputs are sent to other blocks and ultimately
to the device utilizing the FPGA. FPGAs and our mythical city both utilize interconnections
between blocks, wire segments for FPGAs and streets and telephone connections for the
city, that can be flexibly designed to meet changing needs with routers in both cases and
stoplights in one. The final elements in the model with the outside world; I/O cells to the FPGA
as airports, freeways, and long distance telephone lines are to the city. The rest of
this report will explore in greater detail implementations of this basic three-element model.
Configurable Logic Blocks:
The heart of the FPGA lies in the CLBs. CLBs appear in rows and columns within all
FPGAs and implement the logic functions desired by the programmer. Most CLBs accomplish this with a lookup table2. Lookup tables (LUTs) are digital memory arrays that contain truth tables for any logic function that can be implemented by the given number of logic inputs for a CLB. The output of the CLB is then the logical result of the function recorded in the lookup table. In order to program the CLBs, truth tables be loaded into the LUTs of each CLB. Refer to page 3 for an example of the CLB architecture for a Xilinx XC5200 chip model are the mechanisms for interaction with the outside world; I/O cells to the FPGA as airports, freeways, and long distance telephone lines are to the city. The rest of this report will explore in greater detail implementations of this basic three-element model.
Configurable Logic Blocks:
Figures 3 and 45 illustrate the operation of a CLB for the Xilinx XC5200 FPGA chip.
The diagram on the left is of one of the four identical logic cells that constitute each CLB. The
segment labeled F contains a lookup table for four inputs (F4-F1). The trapezoidal objects are 2:1
mutiplexers. The chip enable (CE), clock (CK) and clear (CLR) signals travel to this cell and all
others in the architecture via global long lines. Each cell can be cleared individually or all can be
cleared at once. Each logic cell can implement either a D flip-flop or a latch. When the clock
transitions high, the D flip-flop (FD) passes the output of the programmed logic operation to the
output (Q).
Modern FPGAs
In the previews section the basic building blocks of a FPGA were described. Additionally to these blocks modern FPGAs have additional units that make the design of applications easier and more efficient. Small memories and arithmetic units are difficult to implement on CLBs. Therefore modern FPGAs provide embedded memories and embedded logic blocks for arithmetic calculations. The most common arithmetic calculation is the multiplication, but many other operations can be provided. The advantage of embedded logic blocks are better speed and space. Additionally embedded memories are easier to interface than extern memories. DSP applications are often good targets for implementation on FPGA. Thus manufacturer add embedded block to be useful for implementing DSP functions, e.g. multipliers. Furthermore,
they provide DSP logic designated for streaming data applications. FPGA often communicate
with microprocessors. Because of that reason, embedded processor cores are added to many FPGAs. The main advantage of embedded microprocessors is the reduction of the latency of communication between microprocessor and the FPGA. The Xilinx 4 family has support for additional operations configured by the designer and implemented by CLBs with th auxiliary processing unit (APU) interface. In contrast to embedded processors, soft cores are build directly on the FPGA fabric. The advantages are that they are configurable and the clock can be the same as that of the FPGA.
[attachment=56229]
Abstract:
This report concerns FPGAs (Field Programmable Gate Arrays). The basic FPGA blocks, I/O, CLBs (Combinational Logic Blocks), and routing architecture, are discussed to impart a basic understanding of FPGA operation. The static RAM implementation method for the programming elements of FPGAs is briefly discussed. An in depth investigation of one common static RAM chip, the Xilinx XC5200, providing physical examples of I/O, CLB, and routing configurations used in industry, is included in the body of this report. Strengths and weaknesses of static RAMFPGAs are discussed in the conclusion.
Field-Programmable Gate Arrays (FPGAs) are pre-fabricated silicon devices that can be electrically programmed to become almost any kind of digital circuit or system [2]. They have many advantages over Application Specific Integrated Circuits (ASIC). ASICs are designed for specific application using CAD tools and fabricated at a foundry. Developing an ASIC takes very much time and is expensive. Furthermore, it is not possible to correct errors after fabrication. In contrast to ASICs, FPGAs are configured after fabrication and they also can be reconfigured. This is done with a hardware description language (HDL) which is compiled to a bit stream and downloaded to the FPGA. The disadvantages of FPGAs are that the same application needs more space (transistors) on chip and the application runs slower on a FPGA as modern as the ASIC counterpart. Due to the increase of transistor density FPGA were getting more powerful over the years. On the other hand the development of ASICs was getting slower and more expensive. Therefore FPGAs are increasingly applied to high performance embedded
systems.
History:
The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field programmable), however programmable logic was hard-wired between logic gates.In the late 1980s the Naval Surface Warfare Department funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.Some of the industry’s foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985.Xilinx co-founders Ross Freeman and Bernard Vonderschmitt invented the first commercially viable field programmable gate array in 1985 – the XC2064. The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market. The XC2064 boasted a mere 64 configurable logic blocks (CLBs), with two 3-input lookup tables (LUTs). More than 20 years later, Freeman was entered into the National Inventors Hall of Fame for his invention.Xilinx continued unchallenged and quickly growing from 1985 to the mid-1990s, when competitors sprouted up, eroding significant market-share. By 1993, Actel was serving about 18 percent of the market.The 1990s were an explosive period of time for FPGAs, both in sophistication and the volume of production. In the early 1990s, FPGAs were primarily used in telecommunications and networking. By the end of the decade, FPGAs found their way into consumer, automotive, and industrial applications.
Block Diagram Description:
Xilinx introduced Field programmable gate arrays, or FPGAs, in1985. Figure 1 is a conceptual model of an FPGA. FPGA are constructed of three basic elements: logic blocks, I/O cells, and
interconnection resources. A useful analogy for an FPGA is the layout of a city. The logic
blocks correspond to city blocks that are occupied by different businesses receiving
products from various suppliers within the city, just as the logic blocks receive data
from other logic blocks within the FPGA, and processing those products for consumption by
other firms or end users, just as logic block outputs are sent to other blocks and ultimately
to the device utilizing the FPGA. FPGAs and our mythical city both utilize interconnections
between blocks, wire segments for FPGAs and streets and telephone connections for the
city, that can be flexibly designed to meet changing needs with routers in both cases and
stoplights in one. The final elements in the model with the outside world; I/O cells to the FPGA
as airports, freeways, and long distance telephone lines are to the city. The rest of
this report will explore in greater detail implementations of this basic three-element model.
Configurable Logic Blocks:
The heart of the FPGA lies in the CLBs. CLBs appear in rows and columns within all
FPGAs and implement the logic functions desired by the programmer. Most CLBs accomplish this with a lookup table2. Lookup tables (LUTs) are digital memory arrays that contain truth tables for any logic function that can be implemented by the given number of logic inputs for a CLB. The output of the CLB is then the logical result of the function recorded in the lookup table. In order to program the CLBs, truth tables be loaded into the LUTs of each CLB. Refer to page 3 for an example of the CLB architecture for a Xilinx XC5200 chip model are the mechanisms for interaction with the outside world; I/O cells to the FPGA as airports, freeways, and long distance telephone lines are to the city. The rest of this report will explore in greater detail implementations of this basic three-element model.
Configurable Logic Blocks:
Figures 3 and 45 illustrate the operation of a CLB for the Xilinx XC5200 FPGA chip.
The diagram on the left is of one of the four identical logic cells that constitute each CLB. The
segment labeled F contains a lookup table for four inputs (F4-F1). The trapezoidal objects are 2:1
mutiplexers. The chip enable (CE), clock (CK) and clear (CLR) signals travel to this cell and all
others in the architecture via global long lines. Each cell can be cleared individually or all can be
cleared at once. Each logic cell can implement either a D flip-flop or a latch. When the clock
transitions high, the D flip-flop (FD) passes the output of the programmed logic operation to the
output (Q).
Modern FPGAs
In the previews section the basic building blocks of a FPGA were described. Additionally to these blocks modern FPGAs have additional units that make the design of applications easier and more efficient. Small memories and arithmetic units are difficult to implement on CLBs. Therefore modern FPGAs provide embedded memories and embedded logic blocks for arithmetic calculations. The most common arithmetic calculation is the multiplication, but many other operations can be provided. The advantage of embedded logic blocks are better speed and space. Additionally embedded memories are easier to interface than extern memories. DSP applications are often good targets for implementation on FPGA. Thus manufacturer add embedded block to be useful for implementing DSP functions, e.g. multipliers. Furthermore,
they provide DSP logic designated for streaming data applications. FPGA often communicate
with microprocessors. Because of that reason, embedded processor cores are added to many FPGAs. The main advantage of embedded microprocessors is the reduction of the latency of communication between microprocessor and the FPGA. The Xilinx 4 family has support for additional operations configured by the designer and implemented by CLBs with th auxiliary processing unit (APU) interface. In contrast to embedded processors, soft cores are build directly on the FPGA fabric. The advantages are that they are configurable and the clock can be the same as that of the FPGA.