02-08-2013, 01:03 PM
System-on-chip design methodology in engineering education
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Abstract:
The system-on-chip design methodology is a new paradigm for electrical and computer
engineering education in digital logic and microelectronics. The development of a close
relationship between the undergraduate course sequence in digital logic and behavioral synthesis
and that in electronics and microelectronics has been problematical until now. The system design
issues considered by these two historically distinct course sequences usually did not have very
much in common. The Western Design Center, Inc., Mesa, AZ, USA and the Department of
Electrical and Computer Engineering, Temple University, Philadelphia, PA, USA have now
established the System Chip Design Center to address these issues in engineering education and
the resulting system-on-chip design methodology. The traditional undergraduate sequence in
digital logic consists of three courses: combinational and sequential logic with schematic capture
and a register transfer language; a processor architecture and assembly language programming
course; and finally a hardware description language course. There would also be a three course
undergraduate sequence in electronics: physical devices and electronic circuits; microelectronics;
and finally integrated circuit design and fabrication. In this new paradigm a coupling and cross-
over occurs between these two undergraduate course sequences with lecture materials and the
laboratory assignments that emphasize the target architecture and the reconfigurable environment
of system-on-chip design.
Two Disparate Threads
Undergraduate electrical and computer engineering education in digital logic and microelectronics has developed in
a somewhat disparate manner, until now. Physical integrated circuit (IC) devices are specified electrically and
functionally from the manufacturer. The task of the undergraduate student, as an incipient digital logic designer, has
been to assemble these packaged ICs into a system by noting their electrical device characteristics, such as the
device input and output voltage and current levels, clock and setup timing requirements and propagation delay, and
the intended functionality of the system. The undergraduate student who studies microelectronics considers device
physics and the complexity of IC layout to meet such electrical characteristics, without much concern for logic
system design. However, the new paradigm of the system-on-chip (SOC) design methodology, prevalent now in
commercial design efforts, has forced engineering educators to modify and conjoin these two threads.
The traditional three-course sequence in digital logic begins with Boolean algebra and combinational and
sequential logic. Initially this first course devoted substantial time and resources to manual methods for
combinational logic minimization, such as the Karnaugh map and the Quine-McCluskey technique, using basic logic
gates. Today this course introduces computer-aided-design (CAD) tools with either instructional software or, what
is more prevalent today, student editions of the same CAD tools as used in industry.
A Single Conjoined Thread
An undergraduate student, who would consider an emphasis in both of these threads, quickly notes the disparity in
the treatment of the material. Logic system design issues, prevalent especially in the second and third courses in that
sequence, are left unresolved in the traditional microelectronics and VLSI course sequence. Logic designs are now
parsed in behavioral synthesis as arbitrary tasks in HDL or in a real-time operating system (RTOS), which, although
crucial to the development of complex systems, are not the manner in which traditional undergraduate
microelectronic and VLSI designs are presented. Microelectronic design issues are not presented in any detail in the
traditional undergraduate logic design course sequence. Yet the SOC design methodology now requires that even
the undergraduate microelectronics courses consider such topics as on-chip busing, clock dispersion and signal
propagation in a VLSI device now assembled from preconfigured or hard-core IC components.
A new course sequence in a conjoined thread presents the SOC design methodology in these undergraduate
courses and provides the curriculum synergy that make this new paradigm possible. The focus of this educational
effort is a grant and laboratory provided by The Western Design Center (WDC), Inc., Mesa, AZ, USA: the System
Chip Design Center (SCDC) at the Department of Electrical and Computer Engineering (ECE), Temple University,
Philadelphia, PA, USA.
What’s Different?
What is different in this undergraduate electrical and computer engineering curriculum? It could be said that any
group of undergraduate digital logic and microelectronic engineering educators can assembly such a curriculum, but
there are some unique pieces that have coalesced in ECE at Temple University. These traits seem to be sufficient,
but may be even necessary, to affect this change in engineering education [4].
First, the faculty responsible for the undergraduate digital logic sequence must become aware and convinced that
the SOC paradigm is as much of a revolution in digital design in the 2000s as the introduction of the microprocessor
was in the 1970s. It would also be highly instructive if the faculty were exposed, first hand, to both of these
revolutions! Engineering educators often try to delay the introduction of so-called “new” curricula with the dictum
that undergraduates are burdened with too much material. This had delayed, in many instances, the introduction of
microprocessor courses in undergraduate ECE education. They must also be reasonably well versed in
microelectronics.
[attachment=56926]
Abstract:
The system-on-chip design methodology is a new paradigm for electrical and computer
engineering education in digital logic and microelectronics. The development of a close
relationship between the undergraduate course sequence in digital logic and behavioral synthesis
and that in electronics and microelectronics has been problematical until now. The system design
issues considered by these two historically distinct course sequences usually did not have very
much in common. The Western Design Center, Inc., Mesa, AZ, USA and the Department of
Electrical and Computer Engineering, Temple University, Philadelphia, PA, USA have now
established the System Chip Design Center to address these issues in engineering education and
the resulting system-on-chip design methodology. The traditional undergraduate sequence in
digital logic consists of three courses: combinational and sequential logic with schematic capture
and a register transfer language; a processor architecture and assembly language programming
course; and finally a hardware description language course. There would also be a three course
undergraduate sequence in electronics: physical devices and electronic circuits; microelectronics;
and finally integrated circuit design and fabrication. In this new paradigm a coupling and cross-
over occurs between these two undergraduate course sequences with lecture materials and the
laboratory assignments that emphasize the target architecture and the reconfigurable environment
of system-on-chip design.
Two Disparate Threads
Undergraduate electrical and computer engineering education in digital logic and microelectronics has developed in
a somewhat disparate manner, until now. Physical integrated circuit (IC) devices are specified electrically and
functionally from the manufacturer. The task of the undergraduate student, as an incipient digital logic designer, has
been to assemble these packaged ICs into a system by noting their electrical device characteristics, such as the
device input and output voltage and current levels, clock and setup timing requirements and propagation delay, and
the intended functionality of the system. The undergraduate student who studies microelectronics considers device
physics and the complexity of IC layout to meet such electrical characteristics, without much concern for logic
system design. However, the new paradigm of the system-on-chip (SOC) design methodology, prevalent now in
commercial design efforts, has forced engineering educators to modify and conjoin these two threads.
The traditional three-course sequence in digital logic begins with Boolean algebra and combinational and
sequential logic. Initially this first course devoted substantial time and resources to manual methods for
combinational logic minimization, such as the Karnaugh map and the Quine-McCluskey technique, using basic logic
gates. Today this course introduces computer-aided-design (CAD) tools with either instructional software or, what
is more prevalent today, student editions of the same CAD tools as used in industry.
A Single Conjoined Thread
An undergraduate student, who would consider an emphasis in both of these threads, quickly notes the disparity in
the treatment of the material. Logic system design issues, prevalent especially in the second and third courses in that
sequence, are left unresolved in the traditional microelectronics and VLSI course sequence. Logic designs are now
parsed in behavioral synthesis as arbitrary tasks in HDL or in a real-time operating system (RTOS), which, although
crucial to the development of complex systems, are not the manner in which traditional undergraduate
microelectronic and VLSI designs are presented. Microelectronic design issues are not presented in any detail in the
traditional undergraduate logic design course sequence. Yet the SOC design methodology now requires that even
the undergraduate microelectronics courses consider such topics as on-chip busing, clock dispersion and signal
propagation in a VLSI device now assembled from preconfigured or hard-core IC components.
A new course sequence in a conjoined thread presents the SOC design methodology in these undergraduate
courses and provides the curriculum synergy that make this new paradigm possible. The focus of this educational
effort is a grant and laboratory provided by The Western Design Center (WDC), Inc., Mesa, AZ, USA: the System
Chip Design Center (SCDC) at the Department of Electrical and Computer Engineering (ECE), Temple University,
Philadelphia, PA, USA.
What’s Different?
What is different in this undergraduate electrical and computer engineering curriculum? It could be said that any
group of undergraduate digital logic and microelectronic engineering educators can assembly such a curriculum, but
there are some unique pieces that have coalesced in ECE at Temple University. These traits seem to be sufficient,
but may be even necessary, to affect this change in engineering education [4].
First, the faculty responsible for the undergraduate digital logic sequence must become aware and convinced that
the SOC paradigm is as much of a revolution in digital design in the 2000s as the introduction of the microprocessor
was in the 1970s. It would also be highly instructive if the faculty were exposed, first hand, to both of these
revolutions! Engineering educators often try to delay the introduction of so-called “new” curricula with the dictum
that undergraduates are burdened with too much material. This had delayed, in many instances, the introduction of
microprocessor courses in undergraduate ECE education. They must also be reasonably well versed in
microelectronics.