14-09-2013, 02:38 PM
ARM Introduction
[attachment=58070]
CISC and RISC
CISC
stands for Complex Instruction Set Computer. Most PC's use CPU based on this architecture. For instance Intel and AMD CPU's are based on CISC architectures.
Typically CISC chips have a large amount of different and complex instructions.
The philosophy behind it is that hardware is always faster than software, therefore one should make a powerful instruction set, which provides programmers with assembly instructions to do a lot with short programs
In common CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions
RISC
stands for Reduced Instruction Set Computer
The philosophy behind it is that almost no one uses complex assembly language instructions as used by CISC, and people mostly use compilers which never use complex instructions.
Therefore fewer, simpler and faster instructions would be better, than the large, complex and slower CISC instructions. However, more instructions are needed to accomplish a task.
An other advantage of RISC is that - in theory - because of the more simple instructions, RISC chips require fewer transistors, which makes them easier to design and cheaper to produce.
it's easier to write powerful optimised compilers, since fewer instructions exist.
Introduction
Advanced RISC Machine.
First RISC microprocessor for commercial use.
Market-leader for low-power and cost-sensitive embedded applications.
History
The history of ARM started in 1983, when a company named Acorn Computers was looking for a 16-bit microprocessor for their next desktop machine.
These processors had complex instruction sets that included instructions taking hundreds of cycles to execute, leading to high interrupt latencies.
Acorn decided to design their own processor, in 1985, they released their first 26-bit Acorn RISC Machine (ARM) processor.
It outperformed the Intel 80286 processor that came out at about the same time.
ARM ISA overview
ARM is a RISC architecture.
Like all RISC architectures, the ARM ISA is a load-store one, that is, instructions that process data operate only on registers and are separate from instructions that access memory.
All ARM instructions are 32-bit long and most of them have a regular three-operand encoding.
ARM architecture features a large register file.
ARM architecture facilitates pipelining of instructions.
The Instruction Pipeline
The pipeline has hardware independent stages that
execute one instruction while decoding a second and fetching a third.
The pipeline speeds up the throughput of CPU instructions so effectively that most ARM instructions can be executed in a single cycle.
The pipeline works most efficiently on linear code.
As soon as a branch is encountered, the pipeline is flushed and must be refilled before full execution speed can be resumed.
the pipeline is part of the CPU, the programmer does not have any exposure to it
Pin Function Select Register 0
The PINSEL0 register controls the functions of the pins as per the settings listed in Table.
The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin.
For other functions, direction is controlled automatically.
Alarm Mask
The Alarm Mask Register (AMR) allows the user to mask any of the alarm registers.
Table shows the relationship between the bits in the AMR and the alarms.
For the alarm function, every non-masked alarm register must match the corresponding time counter for an interrupt to be generated.
The interrupt is generated only when the counter comparison first changes from no match to match.
The interrupt is removed when a one is written to the appropriate bit of the Interrupt Location Register (ILR). If
all mask bits are set, then the alarm is disabled.
[attachment=58070]
CISC and RISC
CISC
stands for Complex Instruction Set Computer. Most PC's use CPU based on this architecture. For instance Intel and AMD CPU's are based on CISC architectures.
Typically CISC chips have a large amount of different and complex instructions.
The philosophy behind it is that hardware is always faster than software, therefore one should make a powerful instruction set, which provides programmers with assembly instructions to do a lot with short programs
In common CISC chips are relatively slow (compared to RISC chips) per instruction, but use little (less than RISC) instructions
RISC
stands for Reduced Instruction Set Computer
The philosophy behind it is that almost no one uses complex assembly language instructions as used by CISC, and people mostly use compilers which never use complex instructions.
Therefore fewer, simpler and faster instructions would be better, than the large, complex and slower CISC instructions. However, more instructions are needed to accomplish a task.
An other advantage of RISC is that - in theory - because of the more simple instructions, RISC chips require fewer transistors, which makes them easier to design and cheaper to produce.
it's easier to write powerful optimised compilers, since fewer instructions exist.
Introduction
Advanced RISC Machine.
First RISC microprocessor for commercial use.
Market-leader for low-power and cost-sensitive embedded applications.
History
The history of ARM started in 1983, when a company named Acorn Computers was looking for a 16-bit microprocessor for their next desktop machine.
These processors had complex instruction sets that included instructions taking hundreds of cycles to execute, leading to high interrupt latencies.
Acorn decided to design their own processor, in 1985, they released their first 26-bit Acorn RISC Machine (ARM) processor.
It outperformed the Intel 80286 processor that came out at about the same time.
ARM ISA overview
ARM is a RISC architecture.
Like all RISC architectures, the ARM ISA is a load-store one, that is, instructions that process data operate only on registers and are separate from instructions that access memory.
All ARM instructions are 32-bit long and most of them have a regular three-operand encoding.
ARM architecture features a large register file.
ARM architecture facilitates pipelining of instructions.
The Instruction Pipeline
The pipeline has hardware independent stages that
execute one instruction while decoding a second and fetching a third.
The pipeline speeds up the throughput of CPU instructions so effectively that most ARM instructions can be executed in a single cycle.
The pipeline works most efficiently on linear code.
As soon as a branch is encountered, the pipeline is flushed and must be refilled before full execution speed can be resumed.
the pipeline is part of the CPU, the programmer does not have any exposure to it
Pin Function Select Register 0
The PINSEL0 register controls the functions of the pins as per the settings listed in Table.
The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin.
For other functions, direction is controlled automatically.
Alarm Mask
The Alarm Mask Register (AMR) allows the user to mask any of the alarm registers.
Table shows the relationship between the bits in the AMR and the alarms.
For the alarm function, every non-masked alarm register must match the corresponding time counter for an interrupt to be generated.
The interrupt is generated only when the counter comparison first changes from no match to match.
The interrupt is removed when a one is written to the appropriate bit of the Interrupt Location Register (ILR). If
all mask bits are set, then the alarm is disabled.