08-01-2014, 03:00 PM
Design and Implementation of Efficient Carry Select Adder Using D-Latch
Abstract
Design of area and power efficient high speed adders forms the larger area of research in VLSI design. Adders are most widely used component in designing digital and many high performance circuit like FIR filters, FPGA implementation etc. Carry Select Adder (CSLA) is one of the fastest adders to perform fast arithmetic operations. This paper proposes CSLA using D-latch having reduced area, power as well as delay as compared to regular SQRT CSLA and modified CSLA that uses binary to excess-1 code converter.
Abstract
Design of area and power efficient high speed adders forms the larger area of research in VLSI design. Adders are most widely used component in designing digital and many high performance circuit like FIR filters, FPGA implementation etc. Carry Select Adder (CSLA) is one of the fastest adders to perform fast arithmetic operations. This paper proposes CSLA using D-latch having reduced area, power as well as delay as compared to regular SQRT CSLA and modified CSLA that uses binary to excess-1 code converter.