16-01-2014, 03:34 PM
RISC PROCESSOR
[attachment=59949]
Introduction:
In the mid-1970's advances in semiconductor technology began to reduce the difference in speed between main memory and processor chips. As memory speed increased, and high-level languages displaced assembly language, the major reasons for CISC began to disappear, and computer designers began to look at ways computer performance could be optimized beyond just making faster hardware.
One of their key realizations was that a sequence of simple instructions produces the same results as a sequence of complex instructions, but can be implemented with a simpler (and faster) hardware design (assuming that memory can keep up). Reduced Instruction Set Computers---RISC machines---were the result. The term reduced implies that the number of instructions, addressing modes, and formats are reduced. All the instructions have same size (usually 32 bits) and execute within a single CPU cycle. Moreover only Simple direct and register addressing modes are used.
RISC Architecture
RISC can be defined as the architecture that reduces chip complexity by using simple and less number of instructions.
Features of RISC are
1. Single –cycle execution of all instructions
2. Single-word standard length of all instructions
3. Small number of instructions not to exceed about 128
4. Small number of instructions formats not to exceed about 4
5. Small number of addressing modes not to exceed about 4
6. Memory access by load and store instructions only
7. All operations, except load and store, are register to register, within the CPU.
8. Hardwired control unit
CISC Fundamentals
A CISC system with a large menu of features implies a larger and more complicated decoding subsystem, preceding the complex control logic. Logic signals will usually have to propagate through a considerable number of gates, increasing the duration of delays and slowing down the system. In a microprogrammed environment, increased complexity will directly produce all necessry microoperations and their corresponding control signals to execute an instruction.
Function:
The ALU performs both arithmetic and logical operations and as well as control of transfer instructions. It takes data and acc as inputs to generate output according to the opcode. An execlk is given as input for synchronization and the output is available at positive edge of the execlk. It performs arithmetic and logic instructions directly and control of transfer instructions are performed with the help of control and logic decoder.
Top order module
Function
Let us consider an instance when some information is stored in the memory. Now when the system is switched on, CPU is initialized. In order to fetch an instruction, as a result the program goes to the location in the memory that is pointed out by the program counter. After some instance, the instruction from the memory is put on the data bus. This cycle is called the instruction fetch cycle. The instruction is now available at the data bus. at next instance; the instruction is loaded into the instruction register. This is called the instruction load. In this cycle the 4 msb’s of the instruction are separated and put in the opcode register and are loaded to control unit as well as ALU. The rest of the bits are sent out as Irout. The outputs of the instruction register and the program counter are connected to a mux. During the negative edge of the fetch signal, the output of the instruction register is selected, while the output from the program counter is selected during the positive edge of fetch cycle.
History of VHDL
VHDL stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language. It was developed in the 1980’s as spin-off of a high-speed integrated circuit research project funded by the US department of defense. During the VHSIC program, researchers were confronted with the daunting task of describing circuits of enormous scale (for their time) and of managing very large circuit design problems that involved multiple teams of engineers. With only gate-level tools available, it soon became clear that more structured design methods and tools would be needed.
To meet this challenge, teams of engineers from three companies - IBM, Texas Instruments and Intermetrics — were contracted by the department of defense to complete the specification and implementation of a new language based design description method.
Levels of abstraction (Styles)
VHDL supports many possible styles of design description. These styles differ primarily in how closely they relate to the underlying hardware. When we speak of the different styles of VHDL, then, we are really talking about the differing levels of abstraction possible using the language. To give an example, it is possible to describe a counter circuit in a number of ways. At the lowest level of abstraction, you could use VHDL's hierarchy features to connect a sequence of predefined logic gates and flip-flips to form a counter circuit.
Need for VHDL
The complex and laborious manual procedures for the design of the hardware have paved the way for the development of languages for high –level description of the digital system. This high-level description can serve as documentation for the part as well as an entry point into the design process. The high level description can be processed through various boards, or gate array using the synthesis tools of Hardware Description language us such a language. VHDL was designed as a solution to provide an integrated design and documentation to communicate design data between various levels of abstractions.
[attachment=59949]
Introduction:
In the mid-1970's advances in semiconductor technology began to reduce the difference in speed between main memory and processor chips. As memory speed increased, and high-level languages displaced assembly language, the major reasons for CISC began to disappear, and computer designers began to look at ways computer performance could be optimized beyond just making faster hardware.
One of their key realizations was that a sequence of simple instructions produces the same results as a sequence of complex instructions, but can be implemented with a simpler (and faster) hardware design (assuming that memory can keep up). Reduced Instruction Set Computers---RISC machines---were the result. The term reduced implies that the number of instructions, addressing modes, and formats are reduced. All the instructions have same size (usually 32 bits) and execute within a single CPU cycle. Moreover only Simple direct and register addressing modes are used.
RISC Architecture
RISC can be defined as the architecture that reduces chip complexity by using simple and less number of instructions.
Features of RISC are
1. Single –cycle execution of all instructions
2. Single-word standard length of all instructions
3. Small number of instructions not to exceed about 128
4. Small number of instructions formats not to exceed about 4
5. Small number of addressing modes not to exceed about 4
6. Memory access by load and store instructions only
7. All operations, except load and store, are register to register, within the CPU.
8. Hardwired control unit
CISC Fundamentals
A CISC system with a large menu of features implies a larger and more complicated decoding subsystem, preceding the complex control logic. Logic signals will usually have to propagate through a considerable number of gates, increasing the duration of delays and slowing down the system. In a microprogrammed environment, increased complexity will directly produce all necessry microoperations and their corresponding control signals to execute an instruction.
Function:
The ALU performs both arithmetic and logical operations and as well as control of transfer instructions. It takes data and acc as inputs to generate output according to the opcode. An execlk is given as input for synchronization and the output is available at positive edge of the execlk. It performs arithmetic and logic instructions directly and control of transfer instructions are performed with the help of control and logic decoder.
Top order module
Function
Let us consider an instance when some information is stored in the memory. Now when the system is switched on, CPU is initialized. In order to fetch an instruction, as a result the program goes to the location in the memory that is pointed out by the program counter. After some instance, the instruction from the memory is put on the data bus. This cycle is called the instruction fetch cycle. The instruction is now available at the data bus. at next instance; the instruction is loaded into the instruction register. This is called the instruction load. In this cycle the 4 msb’s of the instruction are separated and put in the opcode register and are loaded to control unit as well as ALU. The rest of the bits are sent out as Irout. The outputs of the instruction register and the program counter are connected to a mux. During the negative edge of the fetch signal, the output of the instruction register is selected, while the output from the program counter is selected during the positive edge of fetch cycle.
History of VHDL
VHDL stands for VHSIC (Very High Speed Integrated Circuit) Hardware Description Language. It was developed in the 1980’s as spin-off of a high-speed integrated circuit research project funded by the US department of defense. During the VHSIC program, researchers were confronted with the daunting task of describing circuits of enormous scale (for their time) and of managing very large circuit design problems that involved multiple teams of engineers. With only gate-level tools available, it soon became clear that more structured design methods and tools would be needed.
To meet this challenge, teams of engineers from three companies - IBM, Texas Instruments and Intermetrics — were contracted by the department of defense to complete the specification and implementation of a new language based design description method.
Levels of abstraction (Styles)
VHDL supports many possible styles of design description. These styles differ primarily in how closely they relate to the underlying hardware. When we speak of the different styles of VHDL, then, we are really talking about the differing levels of abstraction possible using the language. To give an example, it is possible to describe a counter circuit in a number of ways. At the lowest level of abstraction, you could use VHDL's hierarchy features to connect a sequence of predefined logic gates and flip-flips to form a counter circuit.
Need for VHDL
The complex and laborious manual procedures for the design of the hardware have paved the way for the development of languages for high –level description of the digital system. This high-level description can serve as documentation for the part as well as an entry point into the design process. The high level description can be processed through various boards, or gate array using the synthesis tools of Hardware Description language us such a language. VHDL was designed as a solution to provide an integrated design and documentation to communicate design data between various levels of abstractions.