17-03-2014, 10:34 AM
ABSTRACT
This paper presents a background mismatch-calibration method
for a capacitive digital-to-analog-converter (CDAC). The linearity
of a CDAC depends on the mismatch of the capacitors. In a
CDAC, every bit activates the corresponding capacitor-bank (CB).
Therefore, there are the same number of CBs as the number of
bits. In reality, it is very important to match the current CB with
the rest least-significant CBs. The mismatch values of individual
capacitors in CBs from the unit sized-capacitor are not important
since the voltage division is defined by capacitor banks as whole.
If perfect matching among CBs are provided then the correct analog
voltage output is defined by the ratio between the particular
CB and total capacitance-value of CDAC considering the mostsignificant
CBs tuned earlier. The method used in this paper is
based on eliminating the mismatch between CBs rather than tuning
each individual elements of CDAC. Adjusting each capacitor
bank is much simpler and powerful technique to eliminate nonlinearities.
INTRODUCTION
Capacitors are one of the most used circuit components in today’s
CMOS technology [1-3]. They have a great potential of keeping
charges and therefore defining the voltage values in mostly
switched-capacitor circuits. Poly-to-poly (so called analog) capacitors
are the most linear capacitors, at the same time there is
a great effort to provide highly linear capacitors in digital CMOS
technologies [4-6]. This will enable to shrink layout areas and
also eliminate some cost associated with the analog capacitors. It
is also desired to use capacitors with highest density possible without
destroying the mismatch performance. Mismatch of devices is
one of the important research topics in today’s CMOS technology
since three dimensional miniaturization continues [2-3,7-8].
There are very efficient calibration methods proposed in the
literature for self-calibrating error voltages of CDAC or mismatches
of capacitor banks in CDAC [9-19]. One of the most efficient
method was to apply correction voltages based on the measured
mismatches between CBs in CDAC [9]. In this method, initial
background measurement was done to find out the mismatches after
then the corresponding digital control signals are stored. These
digital control signals were applied back to the system during normal
conversion cycle through a resistive string and a calibration capacitor.
Modified version of this method were also proposed with
increased number of calibraction capacitors and resistive-strings
[11,14]. Meanwhile, there were also calibration shown for multistep
converters [12,15]. One interesting idea was using a singlecapacitor
pulse-counting DAC in order to generate precise code
voltage references and then measure/correct the errors based on
these voltages [16]. One other efficient technique was to implement
quasi-passive configuration with segmentation and mismatchshaping
to obtain highly-linear low-power DAC [17]. The last
technique is proposed recently to use non-binary capacitor banks,
which carries errors to the digital domain and finally does correction
in this domain [19].
In this paper, the same measurement-technique is used with
Ref. [9]. However, during the calibration, additional binary-weighted
capacitor-banks are used to calibrate the mismatch of capacitorbanks
in the main capacitive digital-to-analog-converter similar to
Ref. [16]. This method allows to use the smallest capacitor possible
with poor matching in main DAC and still to obtain the best
linearity performance. By this way, there is no additional power
consuming resistor string needed.
This paper presents a background mismatch-calibration method
for a capacitive digital-to-analog-converter (CDAC). The linearity
of a CDAC depends on the mismatch of the capacitors. In a
CDAC, every bit activates the corresponding capacitor-bank (CB).
Therefore, there are the same number of CBs as the number of
bits. In reality, it is very important to match the current CB with
the rest least-significant CBs. The mismatch values of individual
capacitors in CBs from the unit sized-capacitor are not important
since the voltage division is defined by capacitor banks as whole.
If perfect matching among CBs are provided then the correct analog
voltage output is defined by the ratio between the particular
CB and total capacitance-value of CDAC considering the mostsignificant
CBs tuned earlier. The method used in this paper is
based on eliminating the mismatch between CBs rather than tuning
each individual elements of CDAC. Adjusting each capacitor
bank is much simpler and powerful technique to eliminate nonlinearities.
INTRODUCTION
Capacitors are one of the most used circuit components in today’s
CMOS technology [1-3]. They have a great potential of keeping
charges and therefore defining the voltage values in mostly
switched-capacitor circuits. Poly-to-poly (so called analog) capacitors
are the most linear capacitors, at the same time there is
a great effort to provide highly linear capacitors in digital CMOS
technologies [4-6]. This will enable to shrink layout areas and
also eliminate some cost associated with the analog capacitors. It
is also desired to use capacitors with highest density possible without
destroying the mismatch performance. Mismatch of devices is
one of the important research topics in today’s CMOS technology
since three dimensional miniaturization continues [2-3,7-8].
There are very efficient calibration methods proposed in the
literature for self-calibrating error voltages of CDAC or mismatches
of capacitor banks in CDAC [9-19]. One of the most efficient
method was to apply correction voltages based on the measured
mismatches between CBs in CDAC [9]. In this method, initial
background measurement was done to find out the mismatches after
then the corresponding digital control signals are stored. These
digital control signals were applied back to the system during normal
conversion cycle through a resistive string and a calibration capacitor.
Modified version of this method were also proposed with
increased number of calibraction capacitors and resistive-strings
[11,14]. Meanwhile, there were also calibration shown for multistep
converters [12,15]. One interesting idea was using a singlecapacitor
pulse-counting DAC in order to generate precise code
voltage references and then measure/correct the errors based on
these voltages [16]. One other efficient technique was to implement
quasi-passive configuration with segmentation and mismatchshaping
to obtain highly-linear low-power DAC [17]. The last
technique is proposed recently to use non-binary capacitor banks,
which carries errors to the digital domain and finally does correction
in this domain [19].
In this paper, the same measurement-technique is used with
Ref. [9]. However, during the calibration, additional binary-weighted
capacitor-banks are used to calibrate the mismatch of capacitorbanks
in the main capacitive digital-to-analog-converter similar to
Ref. [16]. This method allows to use the smallest capacitor possible
with poor matching in main DAC and still to obtain the best
linearity performance. By this way, there is no additional power
consuming resistor string needed.