17-03-2014, 04:20 PM
Comparing Performance of Common Megafunctions
[attachment=60143]
Introduction
The maximum performance capability of programmable logic devices
(PLDs) has increased dramatically over the last few years. In the past,
high-density PLDs were limited to 33-MHz operation for most
applications. Today, devices with 20,000 to 100,000 gates typically operate
up to 66 MHz and beyond.
The performance of high-density PLDs varies greatly depending on the
device architecture, the design tools used, and the design complexity. As
a result, the only way to fairly test performance between competitive
architectures is to use benchmark designs that eliminate the variability
associated with design complexity and tool efficiency.
This application note summarizes the results of performance tests
comparing Altera® FLEX® 10KA-1 devices against Xilinx XC4000XL-09
devices when implementing pre-optimized functions. Because each
function was optimized for the target architecture, biases associated with
design tool efficiency, routing, and synthesis were eliminated from the
experiment
Proprietary Megafunctions
This experiment tested the performance of Altera FLEX 10KA-1 and
Xilinx XC4000XL-09 devices when implementing pre-optimized functions
created by each company. Altera chose two functions that are commonly
used in typical applications, a multiplier and finite impulse response (FIR)
filter, to use in the experiment. Table 1 shows the devices tested in the
experiment.
Altera FLEX 10KA Devices
The multiplier and FIR filter functions were implemented and
synthesized in FLEX 10KA-1 devices with the MAX+PLUS® II version 8.3
development tool. Timing-driven compilation and the Fast Synthesis style
were turned on for all design compilations. In addition, the speed/area
optimization setting in the MAX+PLUS II software was set to maximize
speed for the FIR filter function. Table 4 shows the difference in
performance when timing-driven compilation was turned on in the
EPF10K30A-1 device.
Results
After compilation, performance rates and logic utilization for each design
were measured using timing analysis in the MAX+PLUS II or XACTstep
M1 software. See “Sample Files” on page 9 for sample Report Files and
Timing Analyzer Output Files generated during the experiment. Table 6
shows the logic elements (LEs) consumed by each device in the
experiment.
[attachment=60143]
Introduction
The maximum performance capability of programmable logic devices
(PLDs) has increased dramatically over the last few years. In the past,
high-density PLDs were limited to 33-MHz operation for most
applications. Today, devices with 20,000 to 100,000 gates typically operate
up to 66 MHz and beyond.
The performance of high-density PLDs varies greatly depending on the
device architecture, the design tools used, and the design complexity. As
a result, the only way to fairly test performance between competitive
architectures is to use benchmark designs that eliminate the variability
associated with design complexity and tool efficiency.
This application note summarizes the results of performance tests
comparing Altera® FLEX® 10KA-1 devices against Xilinx XC4000XL-09
devices when implementing pre-optimized functions. Because each
function was optimized for the target architecture, biases associated with
design tool efficiency, routing, and synthesis were eliminated from the
experiment
Proprietary Megafunctions
This experiment tested the performance of Altera FLEX 10KA-1 and
Xilinx XC4000XL-09 devices when implementing pre-optimized functions
created by each company. Altera chose two functions that are commonly
used in typical applications, a multiplier and finite impulse response (FIR)
filter, to use in the experiment. Table 1 shows the devices tested in the
experiment.
Altera FLEX 10KA Devices
The multiplier and FIR filter functions were implemented and
synthesized in FLEX 10KA-1 devices with the MAX+PLUS® II version 8.3
development tool. Timing-driven compilation and the Fast Synthesis style
were turned on for all design compilations. In addition, the speed/area
optimization setting in the MAX+PLUS II software was set to maximize
speed for the FIR filter function. Table 4 shows the difference in
performance when timing-driven compilation was turned on in the
EPF10K30A-1 device.
Results
After compilation, performance rates and logic utilization for each design
were measured using timing analysis in the MAX+PLUS II or XACTstep
M1 software. See “Sample Files” on page 9 for sample Report Files and
Timing Analyzer Output Files generated during the experiment. Table 6
shows the logic elements (LEs) consumed by each device in the
experiment.