17-03-2014, 05:05 PM
Abstract—As the semiconductor process technology continues
to scale deeper into the nanometer region, the intrinsic
parameter fluctuations will aggressively affect the performance
of future microprocessors. Therefore one of the challenge of
advanced CMOS manufacturing lies in modeling and simulating
the intrinsic parameter fluctuations for accurately assessing
the performance and the yield of the corresponding integrated
circuits (ICs). To investigate the impact of IPF at architecturallevel,
a framework to bridge architecture-level and device-level
simulation will be presented. In this work, the framework
will include intrinsic parameter fluctuation information from
UTB-SOI transistors within the 25 nm and 13 nm technology
node into architectural-level simulation. The impact of discrete
random dopants in the source/drain regions, line edge roughness
and body-thickness variations on a microprocessor cache
memory system will be presented.
I. INTRODUCTION
The International
Technology Roadmap for Semiconductors (ITRS) predicts
that the microelectronic industry will benefit enormously
from MOSFET miniaturization to the nanometer regime
for the next decades. However, the scaling of device size
are approaching fundamental physical limits [1]. One of
the most challenging by-products of feature scaling that is
proving extremely difficult to manage are the increasing
variations of the transistor characteristics due to intrinsic
parameter fluctuations (IPF). This problem is associated with
the fundamental discreteness of charge and matter [2], [3] and
cannot be removed by better processing steps or improved
equipment [4].
It has been experimentally demonstrated at device and
circuit level that with the continuing scaling of the
conventional MOSFETs, IPF will adversely affect circuit
performance [5], [6]. As the process and technology to build
the next generation devices and IC are very complex or still
unavailable, several simulation methodology to investigate
the impact of IPF at circuit-level have been introduced
[7], [8], [9]. However, application of circuit-level simulation
are limited because it is only suitable to investigate circuit
blocks. From architecture-level point of view, investigating
the intrinsic transistor variability is important, because
architectural techniques can control large groups of circuits
(e.g. control circuitry, cache lines or the entire cache) at once.
Evaluation of computer architecture or micro-architecture
is usually done by simulators based on instruction-set or
register-transfer level [10], [11], [12].
Typical simulations study compare the performances
of hardware-enhanced models with a baseline model by
running benchmark programs. These tools also provides
the opportunity to investigate static or dynamic power ,
battery dissipation , compiler development , chip area and
system reliability . Most of these studies requires analytical
MOSFET models or compact-model parameters that do not
fully account IPF effects that is critical for nanometer regime
devices.
In this paper, a framework to bridge architecture-level and
device-level simulation will be presented. This framework
allows modeling of computer architecture using realistic and
physical device emulation. The rest of the paper is organized
as follows. The nature of intrinsic parameter fluctuation
in 6T-SRAM cells based on UTB-SOI MOSFETs will be
presented in Section II. These baseline fault observed will
be used as an input to the fault injection framework. The
methodology for the framework will be described in Section
III. The strategy for fault injection and the cache memory
setup will be elaborated. The benchmark programs used for
the purpose of this study will be presented. Preliminary
result from cache memory simulation injected with intrinsic
parameter fluctuation will be presented in Section IV. The
conclusion of the work is given in Section V.
to scale deeper into the nanometer region, the intrinsic
parameter fluctuations will aggressively affect the performance
of future microprocessors. Therefore one of the challenge of
advanced CMOS manufacturing lies in modeling and simulating
the intrinsic parameter fluctuations for accurately assessing
the performance and the yield of the corresponding integrated
circuits (ICs). To investigate the impact of IPF at architecturallevel,
a framework to bridge architecture-level and device-level
simulation will be presented. In this work, the framework
will include intrinsic parameter fluctuation information from
UTB-SOI transistors within the 25 nm and 13 nm technology
node into architectural-level simulation. The impact of discrete
random dopants in the source/drain regions, line edge roughness
and body-thickness variations on a microprocessor cache
memory system will be presented.
I. INTRODUCTION
The International
Technology Roadmap for Semiconductors (ITRS) predicts
that the microelectronic industry will benefit enormously
from MOSFET miniaturization to the nanometer regime
for the next decades. However, the scaling of device size
are approaching fundamental physical limits [1]. One of
the most challenging by-products of feature scaling that is
proving extremely difficult to manage are the increasing
variations of the transistor characteristics due to intrinsic
parameter fluctuations (IPF). This problem is associated with
the fundamental discreteness of charge and matter [2], [3] and
cannot be removed by better processing steps or improved
equipment [4].
It has been experimentally demonstrated at device and
circuit level that with the continuing scaling of the
conventional MOSFETs, IPF will adversely affect circuit
performance [5], [6]. As the process and technology to build
the next generation devices and IC are very complex or still
unavailable, several simulation methodology to investigate
the impact of IPF at circuit-level have been introduced
[7], [8], [9]. However, application of circuit-level simulation
are limited because it is only suitable to investigate circuit
blocks. From architecture-level point of view, investigating
the intrinsic transistor variability is important, because
architectural techniques can control large groups of circuits
(e.g. control circuitry, cache lines or the entire cache) at once.
Evaluation of computer architecture or micro-architecture
is usually done by simulators based on instruction-set or
register-transfer level [10], [11], [12].
Typical simulations study compare the performances
of hardware-enhanced models with a baseline model by
running benchmark programs. These tools also provides
the opportunity to investigate static or dynamic power ,
battery dissipation , compiler development , chip area and
system reliability . Most of these studies requires analytical
MOSFET models or compact-model parameters that do not
fully account IPF effects that is critical for nanometer regime
devices.
In this paper, a framework to bridge architecture-level and
device-level simulation will be presented. This framework
allows modeling of computer architecture using realistic and
physical device emulation. The rest of the paper is organized
as follows. The nature of intrinsic parameter fluctuation
in 6T-SRAM cells based on UTB-SOI MOSFETs will be
presented in Section II. These baseline fault observed will
be used as an input to the fault injection framework. The
methodology for the framework will be described in Section
III. The strategy for fault injection and the cache memory
setup will be elaborated. The benchmark programs used for
the purpose of this study will be presented. Preliminary
result from cache memory simulation injected with intrinsic
parameter fluctuation will be presented in Section IV. The
conclusion of the work is given in Section V.