17-03-2014, 05:16 PM
Abstract
Abstract— This invited paper overviews the low level
debug support hardware required for an on-chip predeployment
debugging system for sensor networks. The
solution provides significant program and data trace
compression using a low complexity messaging
framework. The architecture targets System-on-Chip
designs with multiple processor cores. The novel
debug support is attached through defined interfaces
making intellectual property re-use more practical.
Synthesis to standard cells shows that the approach is
more compact than conventional solutions. Extensions
to the overviewed architecture are then proposed to
allow support for both reconfigurable circuits and
hybrid circuits that contain a mixture of
reconfigurable and static cores.
1. Introduction
Increased integration has lead to the movement of
the interfaces that were once used extensively for
debugging on-chip. Such changes remove all
attachment points for external development tools [1-3],
leaving system designers with overwhelming design
complexity and unbearable time-to-market pressure
without adequate visibility of the system’s behavior.
These new development challenges cannot be resolved
simply by multiplexing a reduced clock frequency bus
onto dedicated external device pins. The importance of
embedded systems is demonstrated by the modern
automobile’s total dependence on electronics for even
its most basic and essential functionality, such as
opening the doors and braking.
As a consequence of increased complexity in the
presence of reduced system level visibility,
dependability has reduced; a recent study found that 77
percent of electronic failures in cars were due to
software [2]. Detecting and correcting these bugs early
in the product cycle reduces development time and
prevents problems in the field. In complex systems like
control applications and multi-node sensor networks it
is of significant importance to understand and analyze
the behavior in all possible scenarios, thus increasing
the overall system quality. Significant debugging and
verification is required pre-deployment to ensure that
the system is correct, once deployed in applications
such as space or environmental monitoring it may be
impossible to gain physical contact with the node. The
change in design philosophy introduced by System-on-
Chip (SoC) and deep-sub-micron effects provides clear
motivation for a corresponding change in system level
debug support architecture. This work relates to system
level debugging which should not be confused with
either silicon debug or testing. Both typically use
different techniques and normally take place while the
system is idle. Conversely system level debugging
occurs while the system runs and considers the
hardware and software as a collective.
Further increases in system complexity and
advancements in integration technology are reasonable
assumptions. New debug architectures should accept
this by supporting the researched technology that
drives future trends like custom reconfigurable cores
[4] and evolvable hardware [5]. An inevitable
advancement will be the increased use of parallel
processing to balance the demands for computing
resources with low power consumption. The further
reductions in power consumption required by wireless
sensor systems will only be achieved by using
optimized hardware processing cores. Traditional cores
have a fixed architecture; but are unsuitable for sensor
networks as they require the hardware to support a
wide class of algorithms. The only feasible solution is
to engineer reconfigurable hardware that can be either
tailored to each problem or optimize its own
configuration. This will lead to both hybrid systems
containing a mixture of reconfigurable Intellectual
Property (IP) cores and purely reconfigurable systems.
Abstract— This invited paper overviews the low level
debug support hardware required for an on-chip predeployment
debugging system for sensor networks. The
solution provides significant program and data trace
compression using a low complexity messaging
framework. The architecture targets System-on-Chip
designs with multiple processor cores. The novel
debug support is attached through defined interfaces
making intellectual property re-use more practical.
Synthesis to standard cells shows that the approach is
more compact than conventional solutions. Extensions
to the overviewed architecture are then proposed to
allow support for both reconfigurable circuits and
hybrid circuits that contain a mixture of
reconfigurable and static cores.
1. Introduction
Increased integration has lead to the movement of
the interfaces that were once used extensively for
debugging on-chip. Such changes remove all
attachment points for external development tools [1-3],
leaving system designers with overwhelming design
complexity and unbearable time-to-market pressure
without adequate visibility of the system’s behavior.
These new development challenges cannot be resolved
simply by multiplexing a reduced clock frequency bus
onto dedicated external device pins. The importance of
embedded systems is demonstrated by the modern
automobile’s total dependence on electronics for even
its most basic and essential functionality, such as
opening the doors and braking.
As a consequence of increased complexity in the
presence of reduced system level visibility,
dependability has reduced; a recent study found that 77
percent of electronic failures in cars were due to
software [2]. Detecting and correcting these bugs early
in the product cycle reduces development time and
prevents problems in the field. In complex systems like
control applications and multi-node sensor networks it
is of significant importance to understand and analyze
the behavior in all possible scenarios, thus increasing
the overall system quality. Significant debugging and
verification is required pre-deployment to ensure that
the system is correct, once deployed in applications
such as space or environmental monitoring it may be
impossible to gain physical contact with the node. The
change in design philosophy introduced by System-on-
Chip (SoC) and deep-sub-micron effects provides clear
motivation for a corresponding change in system level
debug support architecture. This work relates to system
level debugging which should not be confused with
either silicon debug or testing. Both typically use
different techniques and normally take place while the
system is idle. Conversely system level debugging
occurs while the system runs and considers the
hardware and software as a collective.
Further increases in system complexity and
advancements in integration technology are reasonable
assumptions. New debug architectures should accept
this by supporting the researched technology that
drives future trends like custom reconfigurable cores
[4] and evolvable hardware [5]. An inevitable
advancement will be the increased use of parallel
processing to balance the demands for computing
resources with low power consumption. The further
reductions in power consumption required by wireless
sensor systems will only be achieved by using
optimized hardware processing cores. Traditional cores
have a fixed architecture; but are unsuitable for sensor
networks as they require the hardware to support a
wide class of algorithms. The only feasible solution is
to engineer reconfigurable hardware that can be either
tailored to each problem or optimize its own
configuration. This will lead to both hybrid systems
containing a mixture of reconfigurable Intellectual
Property (IP) cores and purely reconfigurable systems.