17-03-2014, 05:28 PM
Abstract
A 12-bit 20MS/s low power pipelined analog-digital
converter is presented. A front-end sampling network is
proposed to eliminate the need of SHA. Passive
capacitor error-averaging technique (PCEA) and Opamp
sharing scheme are employed to achieve high resolutions
and low power and area. The drawback of conventional
Opamp sharing technique is resolved with polarity
inverting scheme by interchanging the polarity of input
and output of Opamp during different clock phases.
Simulated with 0.5um mix-signal CMOS technology, the
ADC dissipates 71mw from a 5V supply, and achieves a
peak SNDR of 69.8dB with a 0.5MHz full-scale sine
input at 20MS/s.
1. Introduction
Analog-to-digital converters are important building
blocks in a wide variety of applications including data
communications and image signal processing. Low
power and relatively high resolution and speed ADCs are
required for these applications. Pipelined ADCs have
proven to be very efficient architecture to make a best
tradeoff among these requirements.
In a pipelined ADC, the S/H function between
consecutive stages allows a concurrent operation of all
stages, thus, pipelined ADCs can operate at high
sampling rates with high dynamic performance.
However, the achievable accuracy of pipelined ADCs is
limited to 10 bits without the use of trimming or digital
calibration because of component mismatch of current
CMOS process [1] [2]. But trimming is often limited by
its efficiency and cost, and calibration usually needs
complicated circuitry and large power consumption. In
this paper, we use a passive capacitor error-averaging
(PCEA) technique illustrated in [3] to relax the
requirement of capacitor mismatch and achieve a high
resolution. The PCEA only need simple circuitry and is
compatible with the operation of SC network. Compared
with a two-phase-clock conventional implementation,
PCEA takes four clock phases to complete the sampling
and amplification process, while having the same power
efficiency defined by the ratio of total conversion power
to sampling rate.
In this paper, a low power 12-bit 20M/s pipeline ADC
combines with PCEA technique is presented. To obtain
low power consumption, several actions were taken. The
front-end SHA is eliminated by a carefully matched
sampling network. And Opamp sharing scheme are
employed to reduce the number of Opamp used in the
prototype. The drawback of conventional Opamp sharing
technique is resolved with polarity inverting scheme by
interchanging the polarity of input and output of Opamp
during different clock phases.
A 12-bit 20MS/s low power pipelined analog-digital
converter is presented. A front-end sampling network is
proposed to eliminate the need of SHA. Passive
capacitor error-averaging technique (PCEA) and Opamp
sharing scheme are employed to achieve high resolutions
and low power and area. The drawback of conventional
Opamp sharing technique is resolved with polarity
inverting scheme by interchanging the polarity of input
and output of Opamp during different clock phases.
Simulated with 0.5um mix-signal CMOS technology, the
ADC dissipates 71mw from a 5V supply, and achieves a
peak SNDR of 69.8dB with a 0.5MHz full-scale sine
input at 20MS/s.
1. Introduction
Analog-to-digital converters are important building
blocks in a wide variety of applications including data
communications and image signal processing. Low
power and relatively high resolution and speed ADCs are
required for these applications. Pipelined ADCs have
proven to be very efficient architecture to make a best
tradeoff among these requirements.
In a pipelined ADC, the S/H function between
consecutive stages allows a concurrent operation of all
stages, thus, pipelined ADCs can operate at high
sampling rates with high dynamic performance.
However, the achievable accuracy of pipelined ADCs is
limited to 10 bits without the use of trimming or digital
calibration because of component mismatch of current
CMOS process [1] [2]. But trimming is often limited by
its efficiency and cost, and calibration usually needs
complicated circuitry and large power consumption. In
this paper, we use a passive capacitor error-averaging
(PCEA) technique illustrated in [3] to relax the
requirement of capacitor mismatch and achieve a high
resolution. The PCEA only need simple circuitry and is
compatible with the operation of SC network. Compared
with a two-phase-clock conventional implementation,
PCEA takes four clock phases to complete the sampling
and amplification process, while having the same power
efficiency defined by the ratio of total conversion power
to sampling rate.
In this paper, a low power 12-bit 20M/s pipeline ADC
combines with PCEA technique is presented. To obtain
low power consumption, several actions were taken. The
front-end SHA is eliminated by a carefully matched
sampling network. And Opamp sharing scheme are
employed to reduce the number of Opamp used in the
prototype. The drawback of conventional Opamp sharing
technique is resolved with polarity inverting scheme by
interchanging the polarity of input and output of Opamp
during different clock phases.