25-08-2017, 09:32 PM
Abstract
This paper gives an overview over the progress that has
been made by the Heidelberg FPTA group within the field
of analog evolvable hardware. Achievements are the design
of a CMOS configurable transistor array (FPTA), the development
of evolutionary algorithms (EAs) for analog circuit
synthesis and the implementation of a modular framework,
which makes it possible to use various substrates and
simulation models for evolution experiments. The improvement
of the EA is shown by comparing the performance of
three implementations in evolving comparators. Additionally,
results, obtained from the FPTA for the evolution of
oscillators from scratch, are presented as an example for
the successful application of the multi-objective Turtle GA.
Finally, it is shown that a simplified software model of the
Heidelberg FPTA is suitable to assess the real hardware,
indicated by the fact that both substrates perform equally
well in finding good solutions for comparators. This work
aims at creating a customizable, modular framework that
facilitates research on the performance and evolvability of
possible FPTA topologies in the future.
1. Introduction
There is a great need for analog circuits carrying out
complex tasks in a great variety of applications ranging
from simple switches to complex DACs, ADCs or OPs.
The classical way of designing suitable circuits for specific
needs is yet to create a schematic and an according
layout, which are conform with an available target technology.
Once the functionality of the designed circuit is
verified with an analog circuit simulator, a corresponding
prototype can be fabricated. Current design flows provide
a very high degree of reliability on the design process and
the outcome, which is a great advantage. Despite this, in
the digital regime, reconfigurable logic chips, namely field
programmable gate arrays (FPGAs), are gaining more and
more of importance with their increasing speed, complexity
and flexibility.
Contrary to that, field programmable analog arrays
(FPAAs) are to date not very elaborated and only a few
analytic solutions for analog design automation are available
[2, 6]. There are three main reasons that make the design
of powerful FPAAs very difficult: First, the lack of an
analytical language in which the behavior of any analog circuit
can be expressed. Second, it is a very challenging task
to design a reconfigurable analog substrate which provides
both, the flexibility to host a great variety of circuits and sufficient
control over the influence of parasitic effects. Third,
even if therewas yet a substrate fulfilling the latter demands,
it is still challenging to develop algorithms, which are able
to configure or map existing topologies to such a substrate.
As a consequence of this, it is necessary to develop topologies
and algorithms at the same time.
Promising approaches on the algorithmic side are made
by using evolutionary algorithms (EAs) for the—in some
cases—simultaneous synthesis of topology and component
sizing of analog circuits [1, 7, 10–12]. If the focus is set
on the automatic synthesis of complex topologies, developmental
strategies like genetic programming (GP) [8, 13, 16]
or heuristic interconnection of building blocks [9] are successfully
applied. In addition to that, multi-objective EAs
[3, 4] are suitable for taking the numerous variables into account,
that need to be optimized for complex problems like
analog circuit design.
This paper gives an overview over the progress that has
been made by the Heidelberg FPTA group within the field
of analog evolvable hardware. Achievements are the design
of a CMOS configurable transistor array (FPTA), the development
of evolutionary algorithms (EAs) for analog circuit
synthesis and the implementation of a modular framework,
which makes it possible to use various substrates and
simulation models for evolution experiments. The improvement
of the EA is shown by comparing the performance of
three implementations in evolving comparators. Additionally,
results, obtained from the FPTA for the evolution of
oscillators from scratch, are presented as an example for
the successful application of the multi-objective Turtle GA.
Finally, it is shown that a simplified software model of the
Heidelberg FPTA is suitable to assess the real hardware,
indicated by the fact that both substrates perform equally
well in finding good solutions for comparators. This work
aims at creating a customizable, modular framework that
facilitates research on the performance and evolvability of
possible FPTA topologies in the future.
1. Introduction
There is a great need for analog circuits carrying out
complex tasks in a great variety of applications ranging
from simple switches to complex DACs, ADCs or OPs.
The classical way of designing suitable circuits for specific
needs is yet to create a schematic and an according
layout, which are conform with an available target technology.
Once the functionality of the designed circuit is
verified with an analog circuit simulator, a corresponding
prototype can be fabricated. Current design flows provide
a very high degree of reliability on the design process and
the outcome, which is a great advantage. Despite this, in
the digital regime, reconfigurable logic chips, namely field
programmable gate arrays (FPGAs), are gaining more and
more of importance with their increasing speed, complexity
and flexibility.
Contrary to that, field programmable analog arrays
(FPAAs) are to date not very elaborated and only a few
analytic solutions for analog design automation are available
[2, 6]. There are three main reasons that make the design
of powerful FPAAs very difficult: First, the lack of an
analytical language in which the behavior of any analog circuit
can be expressed. Second, it is a very challenging task
to design a reconfigurable analog substrate which provides
both, the flexibility to host a great variety of circuits and sufficient
control over the influence of parasitic effects. Third,
even if therewas yet a substrate fulfilling the latter demands,
it is still challenging to develop algorithms, which are able
to configure or map existing topologies to such a substrate.
As a consequence of this, it is necessary to develop topologies
and algorithms at the same time.
Promising approaches on the algorithmic side are made
by using evolutionary algorithms (EAs) for the—in some
cases—simultaneous synthesis of topology and component
sizing of analog circuits [1, 7, 10–12]. If the focus is set
on the automatic synthesis of complex topologies, developmental
strategies like genetic programming (GP) [8, 13, 16]
or heuristic interconnection of building blocks [9] are successfully
applied. In addition to that, multi-objective EAs
[3, 4] are suitable for taking the numerous variables into account,
that need to be optimized for complex problems like
analog circuit design.