17-03-2014, 08:04 PM
Abstract—Virtual platforms are widely applied for embedded
software protoyping and analysis. We introduce here an
automatic annotation and estimation technique for the dynamic
time analysis of embedded software. The annotation technique
automatically inserts marks into the software, which can later
be identified at assembler code level in order to back-annotate
them with timing or power information. Our graph based
technique applies automated labeling of basic blocks to aid
in efficient construction of basic blocks for the disassembler.
The graph is compacted for efficiency and a novel graph
traversal technique is applied to estimate the flow cost. The
timing estimates are later back annotated to the source code
with the help of identifiers which are then used in SystemC
simulations. Our technique can be easily deployed across
variety of architectures as it is compiler-independent and does
not implement any architecture specific features to estimate the
time. The option to back-annotate the timing estimates avoids
the requirement to recompile the entire model to get the same
information before simulation.
Keywords—Automatic time annotation, CPU-cycle estimation,
graphical representation
I. INTRODUCTION
With increasing design complexity, the early consideration
of software became a crucial factor in electronic systems
design. In this context, the configuration and scaling of
the Hardware-dependent Software (HdS) as an important
interface between application software and hardware became
the focus of multiple investigations throughout the last years.
Today, embedded systems software development is mainly
conducted by virtual system prototyps, in combination with
host compiled simulation based approaches and the application
of instruction set simulators.
Figure 1: Abstraction Levelsl by Schirner et al. [1]
In that context, several approaches for different abstraction
and refinement levels have been introduced through the last
years. As given by Fig.1, a layered approach was presented
in [1], incrementally describing processor modeling with
essential features of task mapping, dynamic scheduling,
interrupt handler, low-level firmware and hardware interrupt
handling. At the highest level, the application is running
natively on the simulation host. At Task Level, an abstract
RTOS model is introduced and processes are refined into
tasks. At the Firmware (FW) and Transaction-Level Modeling
(TLM) refinement steps, hardware abstraction (HAL)
and processor hardware layers are introduced. The FW and
TLM level add models of the external bus communication
and the interrupt handling chain on the software and
hardware side, respectively. Finally, a Bus-Functional Model
(BFM) of the processor includes pin- and cycle-accurate
models of the bus interfaces and the protocol state machines
driving and sampling the external wires.
software protoyping and analysis. We introduce here an
automatic annotation and estimation technique for the dynamic
time analysis of embedded software. The annotation technique
automatically inserts marks into the software, which can later
be identified at assembler code level in order to back-annotate
them with timing or power information. Our graph based
technique applies automated labeling of basic blocks to aid
in efficient construction of basic blocks for the disassembler.
The graph is compacted for efficiency and a novel graph
traversal technique is applied to estimate the flow cost. The
timing estimates are later back annotated to the source code
with the help of identifiers which are then used in SystemC
simulations. Our technique can be easily deployed across
variety of architectures as it is compiler-independent and does
not implement any architecture specific features to estimate the
time. The option to back-annotate the timing estimates avoids
the requirement to recompile the entire model to get the same
information before simulation.
Keywords—Automatic time annotation, CPU-cycle estimation,
graphical representation
I. INTRODUCTION
With increasing design complexity, the early consideration
of software became a crucial factor in electronic systems
design. In this context, the configuration and scaling of
the Hardware-dependent Software (HdS) as an important
interface between application software and hardware became
the focus of multiple investigations throughout the last years.
Today, embedded systems software development is mainly
conducted by virtual system prototyps, in combination with
host compiled simulation based approaches and the application
of instruction set simulators.
Figure 1: Abstraction Levelsl by Schirner et al. [1]
In that context, several approaches for different abstraction
and refinement levels have been introduced through the last
years. As given by Fig.1, a layered approach was presented
in [1], incrementally describing processor modeling with
essential features of task mapping, dynamic scheduling,
interrupt handler, low-level firmware and hardware interrupt
handling. At the highest level, the application is running
natively on the simulation host. At Task Level, an abstract
RTOS model is introduced and processes are refined into
tasks. At the Firmware (FW) and Transaction-Level Modeling
(TLM) refinement steps, hardware abstraction (HAL)
and processor hardware layers are introduced. The FW and
TLM level add models of the external bus communication
and the interrupt handling chain on the software and
hardware side, respectively. Finally, a Bus-Functional Model
(BFM) of the processor includes pin- and cycle-accurate
models of the bus interfaces and the protocol state machines
driving and sampling the external wires.