17-03-2014, 08:49 PM
Abstract —Thermometer-to-binary decoders have become
the bottleneck in Flash analog-to-digital converters. This
paper describes five different 5-bit thermometer-to-binary
decoders which are suitable for flash analog-to-digital
converter in 1.8V, 0.18μm CMOS technology. Comparative
study between these thermometer-to-binary decoders is
done based on power consumption, count of transistors and
delay. The combination of medium power, low transistor
count, more regular structure and shorter critical path makes
the multiplexer-based decoder is a viable option for efficient
Flash ADC design.
Keywords- Fat-tree, Flash ADC, Gray-ROM, ROM,
TC-to-BC Decoder.
I. INTRODUCTION
Flash analog-to-digital converter (ADC) is known for its
high speed operation and simple architecture [1].The ADC
plays an important role between analog and digital signals.
It has the advantage of having very high sampling frequency
and high conversion data rate, but it has the disadvantage
with very large chip area, low resolution and high power
consumption. Flash ADC architecture uses 2N resistors and
2N-1 comparators to convert an N-bit data. In traditional
flash ADC architecture 2N-1 comparators will work in
parallel, which will cause high power consumption.
This work presents analysis of five 5-bit thermometerto-
binary decoders (TC-to-BC decoders) useful in flash
ADC. The authors noticed that indeed the TC -to- BC
decoder was the bottleneck of the ultra-high speed CMOS
flash ADC. Thus, in this paper the authors tried to design
and analyze different types of architectures of 5-bit TC-to-
BC decoders suitable for the ultra-high speed flash ADCs in
terms of power dissipation, number of transistors used and
delay.
This paper is divided into four main parts. In section II,
the architecture of high-speed Flash ADC is reviewed.
Section III considers 5-bit TC-to-BC decoder designs. The
results of simulation obtained are presented in section IV
and the conclusions in section V.
the bottleneck in Flash analog-to-digital converters. This
paper describes five different 5-bit thermometer-to-binary
decoders which are suitable for flash analog-to-digital
converter in 1.8V, 0.18μm CMOS technology. Comparative
study between these thermometer-to-binary decoders is
done based on power consumption, count of transistors and
delay. The combination of medium power, low transistor
count, more regular structure and shorter critical path makes
the multiplexer-based decoder is a viable option for efficient
Flash ADC design.
Keywords- Fat-tree, Flash ADC, Gray-ROM, ROM,
TC-to-BC Decoder.
I. INTRODUCTION
Flash analog-to-digital converter (ADC) is known for its
high speed operation and simple architecture [1].The ADC
plays an important role between analog and digital signals.
It has the advantage of having very high sampling frequency
and high conversion data rate, but it has the disadvantage
with very large chip area, low resolution and high power
consumption. Flash ADC architecture uses 2N resistors and
2N-1 comparators to convert an N-bit data. In traditional
flash ADC architecture 2N-1 comparators will work in
parallel, which will cause high power consumption.
This work presents analysis of five 5-bit thermometerto-
binary decoders (TC-to-BC decoders) useful in flash
ADC. The authors noticed that indeed the TC -to- BC
decoder was the bottleneck of the ultra-high speed CMOS
flash ADC. Thus, in this paper the authors tried to design
and analyze different types of architectures of 5-bit TC-to-
BC decoders suitable for the ultra-high speed flash ADCs in
terms of power dissipation, number of transistors used and
delay.
This paper is divided into four main parts. In section II,
the architecture of high-speed Flash ADC is reviewed.
Section III considers 5-bit TC-to-BC decoder designs. The
results of simulation obtained are presented in section IV
and the conclusions in section V.