29-03-2014, 12:29 PM
SIMULATION OF 16-BIT MICROPROCESSOR
[attachment=60628]
BACKGROUND AND MOTIVATION
For a long time, programming languages such as FORTRAN, Pascal and C
were being used to describe computer programs that were sequential in nature.
However, in the digital design field, designers felt the need for a standard
language to describe digital circuits or a language for a digital modelling.
Subsequently, Hardware Description Language (HDLs) came in to existence.
Two popular HDLs used by many engineers today are VHDL and Verilog.
VHDL, which stands for Very High Speed Integrated Circuit Hardware
description language, was sponsored and developed jointly by the U.S.
Department of Defence and IEEE in the mid-1980s. VHDL, in many respects,
is similar to a regular computer language, such as C
BACKGROUND OF HDL
In order to achieve the objective of this project, an overview of VHDL
methodology was review and researched. Why do designers prefer HDL?
HDLs have many advantages compared to traditional schematic designs.
The design flow shown in Figure 2.1 is typically used by designers who use
HDLs. In any design, specifications are written first. Specifications describe
abstractly the functionality, interface and overall architecture of the circuit of
the digital circuit to be designed. At this point, the designers do not need to
think about how they will implement the circuits. A behavioural description is
then created to analyze the design in terms of the functionality, performance,
compliance to standards, and other high level issues. Behavioural description
is often written with HDLs.
Designs can be described at a very abstract by use of HDLs. Designers can
write their RTL(register transfer level) description without choosing a specific
fabrication technology. If a new technology emerges, designers do not need to
redesign their circuit.
Describing design in HDLs, functional verification of design can be done
early in the design cycle. Since designers work at the RTL level, they can
optimize and modify the RTL description until it meets the desired
functionality. Most designs bugs are eliminated at this point. This cuts down
design cycle time significantly because the chances of hitting a functional bug
at a later time in the gate-level layout is minimised.
KEY COMPONENTS IN VHDL
A VHDL entity (design) has one or more input, output or input-output ports
that are connected (wire) to neighboring systems. An entity is itself composed
of interconnected entities, processors, and components, all which operate
concurrently. Each entity is defined by an architecture, which is composed of
VHDL constructs such as arithmetic, signal assignments, or components
statements. In VHDL, independent processes model
[attachment=60628]
BACKGROUND AND MOTIVATION
For a long time, programming languages such as FORTRAN, Pascal and C
were being used to describe computer programs that were sequential in nature.
However, in the digital design field, designers felt the need for a standard
language to describe digital circuits or a language for a digital modelling.
Subsequently, Hardware Description Language (HDLs) came in to existence.
Two popular HDLs used by many engineers today are VHDL and Verilog.
VHDL, which stands for Very High Speed Integrated Circuit Hardware
description language, was sponsored and developed jointly by the U.S.
Department of Defence and IEEE in the mid-1980s. VHDL, in many respects,
is similar to a regular computer language, such as C
BACKGROUND OF HDL
In order to achieve the objective of this project, an overview of VHDL
methodology was review and researched. Why do designers prefer HDL?
HDLs have many advantages compared to traditional schematic designs.
The design flow shown in Figure 2.1 is typically used by designers who use
HDLs. In any design, specifications are written first. Specifications describe
abstractly the functionality, interface and overall architecture of the circuit of
the digital circuit to be designed. At this point, the designers do not need to
think about how they will implement the circuits. A behavioural description is
then created to analyze the design in terms of the functionality, performance,
compliance to standards, and other high level issues. Behavioural description
is often written with HDLs.
Designs can be described at a very abstract by use of HDLs. Designers can
write their RTL(register transfer level) description without choosing a specific
fabrication technology. If a new technology emerges, designers do not need to
redesign their circuit.
Describing design in HDLs, functional verification of design can be done
early in the design cycle. Since designers work at the RTL level, they can
optimize and modify the RTL description until it meets the desired
functionality. Most designs bugs are eliminated at this point. This cuts down
design cycle time significantly because the chances of hitting a functional bug
at a later time in the gate-level layout is minimised.
KEY COMPONENTS IN VHDL
A VHDL entity (design) has one or more input, output or input-output ports
that are connected (wire) to neighboring systems. An entity is itself composed
of interconnected entities, processors, and components, all which operate
concurrently. Each entity is defined by an architecture, which is composed of
VHDL constructs such as arithmetic, signal assignments, or components
statements. In VHDL, independent processes model