29-10-2012, 04:44 PM
VLSI TEST PRINCIPLES AND ARCHITECTURES
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IMPORTANCE OF TESTING
Following the so-called Moore’s law [Moore 1965], the scale of ICs has doubled
every 18 months. A simple example of this trend is the progression from SSI to VLSI
devices. In the 1980s, the term “VLSI” was used for chips having more than 100,000
transistors and has continued to be used over time to refer to chips with millions
and now hundreds of millions of transistors. In 1986, the first megabit randomaccess
memory (RAM) contained more than 1 million transistors. Microprocessors
produced in 1994 contained more than 3 million transistors [Arthistory 2005]. VLSI
devices with many millions of transistors are commonly used in today’s computers
and electronic appliances. This is a direct result of the steadily decreasing dimensions,
referred to as feature size, of the transistors and interconnecting wires from
tens of microns to tens of nanometers.
TESTING DURING THE VLSI LIFECYCLE
Testing typically consists of applying a set of test stimuli to the inputs of the circuit
under test (CUT) while analyzing the output responses, as illustrated in Figure 1.1
Circuits that produce the correct output responses for all input stimuli pass the
test and are considered to be fault-free. Those circuits that fail to produce a correct
response at any point during the test sequence are assumed to be faulty. Testing is performed at various stages in the lifecycle of a VLSI device, including during the
VLSI development process, the electronic system manufacturing process, and, in
some cases, system-level operation. In this section, we examine these various types
of testing, beginning with the VLSI development process.
VLSI Development Process
The VLSI development process is illustrated in Figure 1.2, where it can be seen that
some form of testing is involved at each stage of the process. Based on a customer or
project need, a VLSI device requirement is determined and formulated as a design
specification. Designers are then responsible for synthesizing a circuit that satisfies
the design specification and for verifying the design. Design verification is a predictive
analysis that ensures that the synthesized design will perform the required
functions when manufactured. When a design error is found, modifications to the
design are necessary and design verification must be repeated. As a result, design
verification can be considered as a form of testing.
Once verified, the VLSI design then goes to fabrication. At the same time, test
engineers develop a test procedure based on the design specification and fault models
associated with the implementation technology. A defect is a flaw or physical
imperfection that may lead to a fault. Due to unavoidable statistical flaws in the
materials and masks used to fabricate ICs, it is impossible for 100% of any particular
kind of IC to be defect-free. Thus, the first testing performed during the manufacturing
process is to test the ICs fabricated on the wafer in order to determine
which devices are defective. The chips that pass the wafer-level test are extracted
and packaged. The packaged devices are retested to eliminate those devices that
may have been damaged during the packaging process or put into defective packages.
Additional testing is used to assure the final quality before going to market.
Design Verification
A VLSI design can be described at different levels of abstraction, as illustrated in
Figure 1.3. The design process is essentially a process of transforming a higher
level description of a design to a lower level description. Starting from a design
specification, a behavioral (architecture) level description is developed in very high
speed integrated circuit hardware description language (VHDL) or Verilog or as
a C program and simulated to determine if it is functionally equivalent to the specification.
The design is then described at the register-transfer level (RTL), which
contains more structural information in terms of the sequential and combinational
logic functions to be performed in the data paths and control circuits. The RTL
description must be verified with respect to the functionality of the behavioral
description before proceeding with synthesis to the logical level.
A logical-level implementation is automatically synthesized from the RTL description
to produce the gate-level design of the circuit. The logical-level implementation
should be verified in as much detail as possible to guarantee the correct functionality
of the final design. In the final step, the logical-level description must be
transformed to a physical-level description in order to obtain the physical placement
and interconnection of the transistors in the VLSI device prior to fabrication.