15-11-2012, 06:25 PM
AN ENHANCED LOW POWER HIGH SPEED ADDER FOR ERROR TOLERANT APPLICATIONS
ERROR TOLERANT ADDER.pptx (Size: 1.1 MB / Downloads: 103)
NEED OF ETA
Increasingly huge data sets and the need for instant response require the adder to be large and fast.
Many different types of fast adders, such as the CSK, CSL and CLA have been developed.
For conventional digital circuit design, speed & power are tradeoff.
Speed α power.
For ETA, a new component to trade-off is introduced: the accuracy.
If the system can accept some error, both power & speed can be improved.
The new trade-off : power-speed-accuracy.
ETA
In the conventional adder circuit, the delay is mainly attributed to the carry propagation chain along the critical path, from LSB to MSB.
Also glitches in the carry propagation chain dissipate a significant proportion of dynamic power dissipation.
Therefore, if the carry propagation can be eliminated or curtailed, a great improvement in speed performance and power consumption can be achieved.
ETA-11M
In the new design, the higher bits should be more accurate than the lower bits as they play a more important role in representing a number.
In this structure, the first three carry generators are cascaded together to generate the carry signals for the two highest blocks.
In this way, the carry signal for the highest block is generated by the preceding 12 bits and the carry signal for the second block is generated by the preceding 8 bits and so on.
CONCLUSION
Thus low-power and high-speed ETA family is to a greater extend more competitive than the conventional adders seen in the market, especially in the low accuracy applications.